Currently atomic and non-atomic smc calls are reusing same HAB channel.
In concurrent scenarios, when these two types of calls are recv at same
time, the message passing will go out of order.
This commit is to separate the channels, by establishing two virtual
channels on a same physical channel.
Change-Id: I776d6407018a06055a2112b07605de78d4953b62
Signed-off-by: Yuhang Ji <quic_yuhaji@quicinc.com>
The current udev rule of LV HAB is
KERNEL=="hab",SUBSYSTEM=="hab", MODE="0666"
The subsystem name of the event device is the class name
when creating the char device. In order to be compatible with
the default hab udev rules, we need to keep the class name of
char devices unchanged.
The current ueventd config of LA HAB is
/dev/hab 0666 system system
Therefore this change has no impact on LA.
Change-Id: Ic9df04b792f97e36454ef4a2ddfef6dfd66ad3c4
Signed-off-by: Zelong Ren <quic_zeloren@quicinc.com>
Its observed that in stress scenarios client is taking
longer time to read response data.
Due to this driver response buffers are getting exhausted
resulting in short of memory and further functional failures.
To mitigate this scenario, increased the timeout from
1.5secs to 15secs to let client consume the rx buffers.
Change-Id: I30c91515eae86753a2c2e9045674a1fe7464074c
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
Enable RUN_QUEUE_STATS to support irq balancer in userspace.
Change-Id: Ifd12e7c76a5adf1d8446e51c6e639fcf37d81388
Signed-off-by: Prajwal V <quic_prajv@quicinc.com>
Enable display_rsc so that bandwidth requests from display
client will go through disp_rsc.
Change-Id: Icb6176f699bf5f4cb031e0667e2ff11d40c5952b
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Add measure_only support for gx clocks, so that consumers can
read their frequencies. Also, change gpu_cc_demet_clk as measure_only
support.
Change-Id: Ibdaa3a92cb1d0ee0acaccfdf10a3e2ebf3c8999e
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
Consider the case of cable disconnect and the dwc3_msm_resume
sequence is running, if between this a spurious irq(dp/dm/pwr_irq) is
received then the irq handler will set resume_pending flag to true
since the in_lpm check will be 0 until that.
Now the core_complete is received, it will queue the resume_work
and check for resume_pending then calls dwc3_msm_resume. So once
sm_work goes into idle it will be stuck waiting for lpm.
Fix this by replacing the direct dwc3_msm_resume with pm_runtime_resume
which will ensure do rpm_resume before calling the resume function.
Change-Id: I05b4b2449d9b1bc32a177adc004e9c098ad58134
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Update the frequency table adding 51.2 MHz frequency to
qupv3_wrap0_s4_clk_src clock as per latest SW plan on VOLCANO.
Change-Id: I920285c60526799e2a146b4e71592b199662c7a2
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
Presently, when CRTSCTS flag is being unset tx_trans_cfg is set to
0x2 and value is printed. Due to this, MSM CTS line signal is being
ignored but from the logs we are not getting enough information
to know this.
Capture more information via logs whenever MSM CTS line signal is
being ignored.
Change-Id: Iec674984ff7906bf8ee02ffa834d84b72b14e6ab
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
Add build configs for Anorak.
Change-Id: I236932bb730049090d08c93b7a04ec985a7082fe
Signed-off-by: Venkata Talluri <quic_vtalluri@quicinc.com>
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Add initial configs to generate the gki and consolidated variants of the
defconfigs meant to support the Anorak target.
Change-Id: Iec2eef0205cc290f3acf65fde773afd32ff68de5
Signed-off-by: Venkata Talluri <quic_vtalluri@quicinc.com>
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Added config support for compilation of
EMAC_MDIO_FE driver.
Change-Id: If0503c74fab0748e5b9a9d666ad8a9d6cf713508
Signed-off-by: Sarosh Hasan <quic_sarohasa@quicinc.com>
Add build configs and bazel files to support TUIVM on Niobe.
Change-Id: I1e81f0b9433defa63b05f286f99c789414aab856
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
This change adds logic to wait for previous SMA read/write opetaion to
complete before processing the next SMA read/write operation.
This will allow the host to process the doorbell CRs in order.
Also added timeout for q2spi_response wait for rx data for 1sec,
to avoid get version stuck issues seen from client side.
Change-Id: I3632a9468674464076ffd97ba97d9df1e8a47a8b
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
This change does refactor of code to move CR headers and
error bytes to array in qup_q2spi_cr_header_event structure.
Change-Id: I9155f08c383f4f94eb50996581c1fc79a4e71520
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
To support split /dev/hab requirement, we need to add
hab group nodes for different mmid groups.
To provide backward compatibility, we will still keep the
default /dev/hab node.
Change-Id: I8d55f2fcfac009d9dcd89dbf755e4d6afc8ab999
Signed-off-by: Zelong Ren <quic_zeloren@quicinc.com>
