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q2spi-msm-geni: Refactor CR headers and error bytes

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This change does refactor of code to move CR headers and
error bytes to array in qup_q2spi_cr_header_event structure.

Change-Id: I9155f08c383f4f94eb50996581c1fc79a4e71520
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
This commit is contained in:
Visweswara Tanuku 2024-04-09 20:54:14 -07:00 committed by Pragaspathi Thilagaraj
parent 407aabfdaa
commit 19d5ec47ff
4 changed files with 29 additions and 69 deletions
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8
drivers/dma/qcom/msm_gpi.c
View File

@ -2445,12 +2445,12 @@ gpi_process_xfer_q2spi_cr_header(struct gpii_chan *gpii_chan,
GPII_VERB(gpii_ptr, gpii_chan->chid,
"code:0x%x type:0x%x hdr_0:0x%x hrd_1:0x%x hrd_2:0x%x hdr3:0x%x\n",
q2spi_cr_header_event->code, q2spi_cr_header_event->type,
q2spi_cr_header_event->cr_hdr_0, q2spi_cr_header_event->cr_hdr_1,
q2spi_cr_header_event->cr_hdr_2, q2spi_cr_header_event->cr_hdr_3);
q2spi_cr_header_event->cr_hdr[0], q2spi_cr_header_event->cr_hdr[1],
q2spi_cr_header_event->cr_hdr[2], q2spi_cr_header_event->cr_hdr[3]);
GPII_VERB(gpii_ptr, gpii_chan->chid,
"cr_byte_0:0x%x cr_byte_1:0x%x cr_byte_2:0x%x cr_byte_3h:0x%x\n",
q2spi_cr_header_event->cr_ed_byte_0, q2spi_cr_header_event->cr_ed_byte_1,
q2spi_cr_header_event->cr_ed_byte_2, q2spi_cr_header_event->cr_ed_byte_3);
q2spi_cr_header_event->cr_ed_byte[0], q2spi_cr_header_event->cr_ed_byte[1],
q2spi_cr_header_event->cr_ed_byte[2], q2spi_cr_header_event->cr_ed_byte[3]);
GPII_VERB(gpii_ptr, gpii_chan->chid, "code:0x%x\n", q2spi_cr_header_event->code);
GPII_VERB(gpii_ptr, gpii_chan->chid,
"cr_byte_0_len:0x%x cr_byte_0_err:0x%x type:0x%x ch_id:0x%x\n",

26
drivers/spi/q2spi-gsi.c
View File

@ -685,27 +685,11 @@ void q2spi_gsi_ch_ev_cb(struct dma_chan *ch, struct msm_gpi_cb const *cb, void *
q2spi_cr_hdr_event = &cb->q2spi_cr_header_event;
num_crs = q2spi_cr_hdr_event->byte0_len;
for (i = 0; i < num_crs; i++) {
if (i == 0) {
if (q2spi_cr_hdr_event->cr_hdr_0 == CR_ADDR_LESS_RD)
atomic_inc(&q2spi->doorbell_pending);
if (q2spi_cr_hdr_event->cr_hdr_0 == CR_BULK_ACCESS_STATUS)
atomic_dec(&q2spi->doorbell_pending);
} else if (i == 1) {
if (q2spi_cr_hdr_event->cr_hdr_1 == CR_ADDR_LESS_RD)
atomic_inc(&q2spi->doorbell_pending);
if (q2spi_cr_hdr_event->cr_hdr_1 == CR_BULK_ACCESS_STATUS)
atomic_dec(&q2spi->doorbell_pending);
} else if (i == 2) {
if (q2spi_cr_hdr_event->cr_hdr_2 == CR_ADDR_LESS_RD)
atomic_inc(&q2spi->doorbell_pending);
if (q2spi_cr_hdr_event->cr_hdr_2 == CR_BULK_ACCESS_STATUS)
atomic_dec(&q2spi->doorbell_pending);
} else if (i == 3) {
if (q2spi_cr_hdr_event->cr_hdr_3 == CR_ADDR_LESS_RD)
atomic_inc(&q2spi->doorbell_pending);
if (q2spi_cr_hdr_event->cr_hdr_3 == CR_BULK_ACCESS_STATUS)
atomic_dec(&q2spi->doorbell_pending);
}
if (q2spi_cr_hdr_event->cr_hdr[i] == CR_ADDR_LESS_RD)
atomic_inc(&q2spi->doorbell_pending);
if (q2spi_cr_hdr_event->cr_hdr[i] == CR_BULK_ACCESS_STATUS)
atomic_dec(&q2spi->doorbell_pending);
}
Q2SPI_DEBUG(q2spi, "%s GSI doorbell event, db_pending:%d\n",
__func__, atomic_read(&q2spi->doorbell_pending));

54
drivers/spi/q2spi-msm-geni.c
View File

@ -975,52 +975,34 @@ struct q2spi_cr_packet *q2spi_prepare_cr_pkt(struct q2spi_geni *q2spi)
spin_lock_irqsave(&q2spi->cr_queue_lock, flags);
q2spi_cr_pkt->num_valid_crs = q2spi_cr_hdr_event->byte0_len;
Q2SPI_DEBUG(q2spi, "%s q2spi_cr_pkt:%p hdr_0:0x%x no_of_crs=%d\n", __func__,
q2spi_cr_pkt, q2spi_cr_hdr_event->cr_hdr_0, q2spi_cr_pkt->num_valid_crs);
q2spi_cr_pkt, q2spi_cr_hdr_event->cr_hdr[0], q2spi_cr_pkt->num_valid_crs);
if (q2spi_cr_hdr_event->byte0_err)
Q2SPI_DEBUG(q2spi, "%s Error: q2spi_cr_hdr_event->byte0_err=%d\n",
__func__, q2spi_cr_hdr_event->byte0_err);
if (q2spi_cr_hdr_event->cr_hdr_0 == 0xF) {
q2spi_cr_pkt->ext_cr_hdr.cmd = (q2spi_cr_hdr_event->cr_hdr_0) & 0xF;
q2spi_cr_pkt->ext_cr_hdr.dw_len = (q2spi_cr_hdr_event->cr_hdr_0 >> 4) & 0x3;
q2spi_cr_pkt->ext_cr_hdr.parity = (q2spi_cr_hdr_event->cr_hdr_0 >> 7) & 0x1;
}
for (i = 0; i < q2spi_cr_pkt->num_valid_crs; i++) {
if (i == 0) {
Q2SPI_DEBUG(q2spi, "%s hdr_0:0x%x\n",
__func__, q2spi_cr_hdr_event->cr_hdr_0);
q2spi_cr_pkt->cr_hdr[i].cmd = (q2spi_cr_hdr_event->cr_hdr_0) & 0xF;
q2spi_cr_pkt->cr_hdr[i].flow = (q2spi_cr_hdr_event->cr_hdr_0 >> 4) & 0x1;
q2spi_cr_pkt->cr_hdr[i].type = (q2spi_cr_hdr_event->cr_hdr_0 >> 5) & 0x3;
q2spi_cr_pkt->cr_hdr[i].parity = (q2spi_cr_hdr_event->cr_hdr_0 >> 7) & 0x1;
} else if (i == 1) {
Q2SPI_DEBUG(q2spi, "%s hdr_1:0x%x\n",
__func__, q2spi_cr_hdr_event->cr_hdr_1);
q2spi_cr_pkt->cr_hdr[i].cmd = (q2spi_cr_hdr_event->cr_hdr_1) & 0xF;
q2spi_cr_pkt->cr_hdr[i].flow = (q2spi_cr_hdr_event->cr_hdr_1 >> 4) & 0x1;
q2spi_cr_pkt->cr_hdr[i].type = (q2spi_cr_hdr_event->cr_hdr_1 >> 5) & 0x3;
q2spi_cr_pkt->cr_hdr[i].parity = (q2spi_cr_hdr_event->cr_hdr_1 >> 7) & 0x1;
} else if (i == 2) {
Q2SPI_DEBUG(q2spi, "%s hdr_2:0x%x\n",
__func__, q2spi_cr_hdr_event->cr_hdr_2);
q2spi_cr_pkt->cr_hdr[i].cmd = (q2spi_cr_hdr_event->cr_hdr_2) & 0xF;
q2spi_cr_pkt->cr_hdr[i].flow = (q2spi_cr_hdr_event->cr_hdr_2 >> 4) & 0x1;
q2spi_cr_pkt->cr_hdr[i].type = (q2spi_cr_hdr_event->cr_hdr_2 >> 5) & 0x3;
q2spi_cr_pkt->cr_hdr[i].parity = (q2spi_cr_hdr_event->cr_hdr_2 >> 7) & 0x1;
} else if (i == 3) {
Q2SPI_DEBUG(q2spi, "%s hdr_3:0x%x\n",
__func__, q2spi_cr_hdr_event->cr_hdr_3);
q2spi_cr_pkt->cr_hdr[i].cmd = (q2spi_cr_hdr_event->cr_hdr_3) & 0xF;
q2spi_cr_pkt->cr_hdr[i].flow = (q2spi_cr_hdr_event->cr_hdr_3 >> 4) & 0x1;
q2spi_cr_pkt->cr_hdr[i].type = (q2spi_cr_hdr_event->cr_hdr_3 >> 5) & 0x3;
q2spi_cr_pkt->cr_hdr[i].parity = (q2spi_cr_hdr_event->cr_hdr_3 >> 7) & 0x1;
}
Q2SPI_DEBUG(q2spi, "%s hdr_[%d]:0x%x\n",
__func__, i, q2spi_cr_hdr_event->cr_hdr[i]);
q2spi_cr_pkt->cr_hdr[i].cmd = (q2spi_cr_hdr_event->cr_hdr[i]) & 0xF;
q2spi_cr_pkt->cr_hdr[i].flow = (q2spi_cr_hdr_event->cr_hdr[i] >> 4) & 0x1;
q2spi_cr_pkt->cr_hdr[i].type = (q2spi_cr_hdr_event->cr_hdr[i] >> 5) & 0x3;
q2spi_cr_pkt->cr_hdr[i].parity = (q2spi_cr_hdr_event->cr_hdr[i] >> 7) & 0x1;
Q2SPI_DEBUG(q2spi, "%s CR HDR[%d] cmd/opcode:%d C_flow:%d type:%d parity:%d\n",
__func__, i, q2spi_cr_pkt->cr_hdr[i].cmd,
q2spi_cr_pkt->cr_hdr[i].flow, q2spi_cr_pkt->cr_hdr[i].type,
q2spi_cr_pkt->cr_hdr[i].parity);
if ((q2spi_cr_hdr_event->cr_hdr[i] & 0xF) == CR_EXTENSION) {
q2spi_cr_pkt->ext_cr_hdr.cmd = (q2spi_cr_hdr_event->cr_hdr[i]) & 0xF;
q2spi_cr_pkt->ext_cr_hdr.dw_len =
(q2spi_cr_hdr_event->cr_hdr[i] >> 4) & 0x3;
q2spi_cr_pkt->ext_cr_hdr.parity =
(q2spi_cr_hdr_event->cr_hdr[i] >> 7) & 0x1;
Q2SPI_DEBUG(q2spi, "%s CR EXT HDR[%d] cmd/opcode:%d dw_len:%d parity:%d\n",
__func__, i, q2spi_cr_pkt->ext_cr_hdr.cmd,
q2spi_cr_pkt->ext_cr_hdr.dw_len,
q2spi_cr_pkt->ext_cr_hdr.parity);
}
}
ptr = (u8 *)q2spi->db_xfer->rx_buf;
for (i = 0; i < q2spi_cr_pkt->num_valid_crs; i++) {

10
include/linux/msm_gpi.h
View File

@ -275,14 +275,8 @@ struct msm_gpi_error_log {
};
struct __packed qup_q2spi_cr_header_event {
u32 cr_hdr_0 : 8;
u32 cr_hdr_1 : 8;
u32 cr_hdr_2 : 8;
u32 cr_hdr_3 : 8;
u32 cr_ed_byte_0 : 8;
u32 cr_ed_byte_1 : 8;
u32 cr_ed_byte_2 : 8;
u32 cr_ed_byte_3 : 8;
u8 cr_hdr[4];
u8 cr_ed_byte[4];
u32 reserved0 : 24;
u8 code : 8;
u32 byte0_len : 4;