Merge "interconnect: qcom: Enable qos programming for VOLCANO"
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*/
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@ -35,7 +35,7 @@ static struct qcom_icc_qosbox qhm_qup1_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -57,7 +57,7 @@ static struct qcom_icc_qosbox xm_ufs_mem_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -79,7 +79,7 @@ static struct qcom_icc_qosbox xm_usb3_0_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -101,7 +101,7 @@ static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -123,7 +123,7 @@ static struct qcom_icc_qosbox qhm_qspi_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -145,7 +145,7 @@ static struct qcom_icc_qosbox qhm_qup0_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -166,8 +166,8 @@ static struct qcom_icc_qosbox qxm_crypto_qos = {
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.offsets = { 0x15000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -188,8 +188,8 @@ static struct qcom_icc_qosbox qxm_ipa_qos = {
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.offsets = { 0x16000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -211,7 +211,7 @@ static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -233,7 +233,7 @@ static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -255,7 +255,7 @@ static struct qcom_icc_qosbox xm_sdc1_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -277,7 +277,7 @@ static struct qcom_icc_qosbox xm_sdc2_qos = {
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -426,7 +426,7 @@ static struct qcom_icc_qosbox qnm_gpu_qos = {
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.offsets = { 0x31000, 0x71000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -504,7 +504,7 @@ static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
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.offsets = { 0x35000, 0x75000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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@ -526,7 +526,7 @@ static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
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.offsets = { 0x37000, 0x77000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -565,6 +565,28 @@ static struct qcom_icc_node qnm_pcie = {
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xf9000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_snoc_gc = {
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.name = "qnm_snoc_gc",
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.id = MASTER_SNOC_GC_MEM_NOC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_snoc_gc_qos,
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.num_links = 1,
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.links = { SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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@ -646,9 +668,9 @@ static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
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.num_ports = 1,
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.offsets = { 0x2a000 },
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.config = &(struct qos_config) {
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.prio = 4,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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.prio = 5,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -774,9 +796,9 @@ static struct qcom_icc_qosbox xm_pcie3_0_qos = {
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.num_ports = 1,
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.offsets = { 0xb000 },
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.config = &(struct qos_config) {
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.prio = 3,
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -796,9 +818,9 @@ static struct qcom_icc_qosbox xm_pcie3_1_qos = {
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.num_ports = 1,
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.offsets = { 0xc000 },
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.config = &(struct qos_config) {
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.prio = 3,
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 0,
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.prio_fwd_disable = 1,
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},
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};
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@ -833,6 +855,94 @@ static struct qcom_icc_node qnm_aggre2_noc = {
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_qosbox qnm_apss_noc_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x1c000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qnm_apss_noc = {
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.name = "qnm_apss_noc",
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.id = MASTER_APSS_NOC,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_apss_noc_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_qosbox qnm_cnoc_data_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x1d000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qnm_cnoc_data = {
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.name = "qnm_cnoc_data",
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.id = MASTER_CNOC_SNOC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_cnoc_data_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_SF },
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};
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static struct qcom_icc_qosbox qxm_pimem_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x1e000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node qxm_pimem = {
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.name = "qxm_pimem",
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.id = MASTER_PIMEM,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qxm_pimem_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_GC },
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};
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static struct qcom_icc_qosbox xm_gic_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0x1f000 },
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.config = &(struct qos_config) {
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.prio = 2,
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.urg_fwd = 0,
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.prio_fwd_disable = 1,
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},
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};
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static struct qcom_icc_node xm_gic = {
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.name = "xm_gic",
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.id = MASTER_GIC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &xm_gic_qos,
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.num_links = 1,
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.links = { SLAVE_SNOC_GEM_NOC_GC },
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};
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static struct qcom_icc_node qnm_mnoc_hf_disp = {
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.name = "qnm_mnoc_hf_disp",
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.id = MASTER_MNOC_HF_MEM_NOC_DISP,
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@ -1490,6 +1600,16 @@ static struct qcom_icc_node srvc_pcie_aggre_noc = {
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.num_links = 0,
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};
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static struct qcom_icc_node qns_gemnoc_gc = {
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.name = "qns_gemnoc_gc",
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.id = SLAVE_SNOC_GEM_NOC_GC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { MASTER_SNOC_GC_MEM_NOC },
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};
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static struct qcom_icc_node qns_gemnoc_sf = {
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.name = "qns_gemnoc_sf",
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.id = SLAVE_SNOC_GEM_NOC_SF,
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@ -1650,22 +1770,30 @@ static struct qcom_icc_bcm bcm_sh1 = {
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.name = "SH1",
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.voter_idx = VOTER_IDX_HLOS,
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.enable_mask = 0x1,
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.num_nodes = 13,
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.num_nodes = 14,
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.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
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&chm_apps, &qnm_gpu,
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&qnm_mdsp, &qnm_mnoc_hf,
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&qnm_mnoc_sf, &qnm_nsp_gemnoc,
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&qnm_pcie, &qnm_snoc_sf,
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&qxm_wlan_q6, &qns_gem_noc_cnoc,
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&qns_pcie },
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&qnm_pcie, &qnm_snoc_gc,
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&qnm_snoc_sf, &qxm_wlan_q6,
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&qns_gem_noc_cnoc, &qns_pcie },
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};
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.voter_idx = VOTER_IDX_HLOS,
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.keepalive = true,
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.num_nodes = 2,
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.nodes = { &qns_gemnoc_gc, &qns_gemnoc_sf },
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};
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static struct qcom_icc_bcm bcm_sn1 = {
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.name = "SN1",
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.voter_idx = VOTER_IDX_HLOS,
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.enable_mask = 0x1,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_sf },
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.nodes = { &qxm_pimem },
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};
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static struct qcom_icc_bcm bcm_sn2 = {
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@ -1924,6 +2052,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = {
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[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
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[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
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[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
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[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
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[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
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[MASTER_WLAN_Q6] = &qxm_wlan_q6,
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[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
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@ -2085,6 +2214,7 @@ static struct qcom_icc_desc volcano_pcie_anoc = {
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static struct qcom_icc_bcm *system_noc_bcms[] = {
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&bcm_sn0,
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&bcm_sn1,
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&bcm_sn2,
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&bcm_sn3,
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};
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@ -2092,6 +2222,11 @@ static struct qcom_icc_bcm *system_noc_bcms[] = {
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static struct qcom_icc_node *system_noc_nodes[] = {
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[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
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[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
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[MASTER_APSS_NOC] = &qnm_apss_noc,
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[MASTER_CNOC_SNOC] = &qnm_cnoc_data,
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[MASTER_PIMEM] = &qxm_pimem,
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[MASTER_GIC] = &xm_gic,
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[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
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[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
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};
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_VOLCANO_H
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@ -16,40 +16,45 @@
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#define MASTER_QUP_1 7
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#define MASTER_A1NOC_SNOC 8
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#define MASTER_A2NOC_SNOC 9
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#define MASTER_CAMNOC_HF 10
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#define MASTER_CAMNOC_ICP 11
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#define MASTER_CAMNOC_SF 12
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#define MASTER_GEM_NOC_CNOC 13
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#define MASTER_GEM_NOC_PCIE_SNOC 14
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#define MASTER_GFX3D 15
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#define MASTER_LPASS_GEM_NOC 16
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#define MASTER_MDP 17
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#define MASTER_MSS_PROC 18
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#define MASTER_MNOC_HF_MEM_NOC 19
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#define MASTER_MNOC_SF_MEM_NOC 20
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#define MASTER_COMPUTE_NOC 21
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#define MASTER_ANOC_PCIE_GEM_NOC 22
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#define MASTER_SNOC_SF_MEM_NOC 23
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#define MASTER_VIDEO 24
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||||
#define MASTER_CNOC_CFG 25
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||||
#define MASTER_CNOC_MNOC_HF_CFG 26
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||||
#define MASTER_PCIE_ANOC_CFG 27
|
||||
#define MASTER_CNOC_MNOC_SF_CFG 28
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||||
#define MASTER_QUP_CORE_0 29
|
||||
#define MASTER_QUP_CORE_1 30
|
||||
#define MASTER_CRYPTO 31
|
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#define MASTER_IPA 32
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#define MASTER_LPASS_PROC 33
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#define MASTER_CDSP_PROC 34
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#define MASTER_WLAN_Q6 35
|
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#define MASTER_PCIE_0 36
|
||||
#define MASTER_PCIE_1 37
|
||||
#define MASTER_QDSS_ETR 38
|
||||
#define MASTER_QDSS_ETR_1 39
|
||||
#define MASTER_SDCC_1 40
|
||||
#define MASTER_SDCC_2 41
|
||||
#define MASTER_UFS_MEM 42
|
||||
#define MASTER_USB3_0 43
|
||||
#define MASTER_APSS_NOC 10
|
||||
#define MASTER_CAMNOC_HF 11
|
||||
#define MASTER_CAMNOC_ICP 12
|
||||
#define MASTER_CAMNOC_SF 13
|
||||
#define MASTER_CNOC_SNOC 14
|
||||
#define MASTER_GEM_NOC_CNOC 15
|
||||
#define MASTER_GEM_NOC_PCIE_SNOC 16
|
||||
#define MASTER_GFX3D 17
|
||||
#define MASTER_LPASS_GEM_NOC 18
|
||||
#define MASTER_MDP 19
|
||||
#define MASTER_MSS_PROC 20
|
||||
#define MASTER_MNOC_HF_MEM_NOC 21
|
||||
#define MASTER_MNOC_SF_MEM_NOC 22
|
||||
#define MASTER_COMPUTE_NOC 23
|
||||
#define MASTER_ANOC_PCIE_GEM_NOC 24
|
||||
#define MASTER_SNOC_GC_MEM_NOC 25
|
||||
#define MASTER_SNOC_SF_MEM_NOC 26
|
||||
#define MASTER_VIDEO 27
|
||||
#define MASTER_CNOC_CFG 28
|
||||
#define MASTER_CNOC_MNOC_HF_CFG 29
|
||||
#define MASTER_PCIE_ANOC_CFG 30
|
||||
#define MASTER_CNOC_MNOC_SF_CFG 31
|
||||
#define MASTER_QUP_CORE_0 32
|
||||
#define MASTER_QUP_CORE_1 33
|
||||
#define MASTER_CRYPTO 34
|
||||
#define MASTER_IPA 35
|
||||
#define MASTER_LPASS_PROC 36
|
||||
#define MASTER_CDSP_PROC 37
|
||||
#define MASTER_PIMEM 38
|
||||
#define MASTER_WLAN_Q6 39
|
||||
#define MASTER_GIC 40
|
||||
#define MASTER_PCIE_0 41
|
||||
#define MASTER_PCIE_1 42
|
||||
#define MASTER_QDSS_ETR 43
|
||||
#define MASTER_QDSS_ETR_1 44
|
||||
#define MASTER_SDCC_1 45
|
||||
#define MASTER_SDCC_2 46
|
||||
#define MASTER_UFS_MEM 47
|
||||
#define MASTER_USB3_0 48
|
||||
#define SLAVE_EBI1 512
|
||||
#define SLAVE_AHB2PHY_SOUTH 513
|
||||
#define SLAVE_AHB2PHY_NORTH 514
|
||||
@ -89,35 +94,36 @@
|
||||
#define SLAVE_A1NOC_SNOC 548
|
||||
#define SLAVE_A2NOC_SNOC 549
|
||||
#define SLAVE_GEM_NOC_CNOC 550
|
||||
#define SLAVE_SNOC_GEM_NOC_SF 551
|
||||
#define SLAVE_LLCC 552
|
||||
#define SLAVE_LPASS_GEM_NOC 553
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 554
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 555
|
||||
#define SLAVE_CDSP_MEM_NOC 556
|
||||
#define SLAVE_MEM_NOC_PCIE_SNOC 557
|
||||
#define SLAVE_ANOC_PCIE_GEM_NOC 558
|
||||
#define SLAVE_APPSS 559
|
||||
#define SLAVE_CNOC_CFG 560
|
||||
#define SLAVE_DDRSS_CFG 561
|
||||
#define SLAVE_CNOC_MNOC_HF_CFG 562
|
||||
#define SLAVE_CNOC_MNOC_SF_CFG 563
|
||||
#define SLAVE_NSP_QTB_CFG 564
|
||||
#define SLAVE_PCIE_ANOC_CFG 565
|
||||
#define SLAVE_WLAN_Q6_THROTTLE_CFG 566
|
||||
#define SLAVE_QUP_CORE_0 567
|
||||
#define SLAVE_QUP_CORE_1 568
|
||||
#define SLAVE_IMEM 569
|
||||
#define SLAVE_PIMEM 570
|
||||
#define SLAVE_SERVICE_CNOC_CFG 571
|
||||
#define SLAVE_SERVICE_CNOC 572
|
||||
#define SLAVE_SERVICE_MNOC_HF 573
|
||||
#define SLAVE_SERVICE_MNOC_SF 574
|
||||
#define SLAVE_SERVICE_PCIE_ANOC 575
|
||||
#define SLAVE_PCIE_0 576
|
||||
#define SLAVE_PCIE_1 577
|
||||
#define SLAVE_QDSS_STM 578
|
||||
#define SLAVE_TCU 579
|
||||
#define SLAVE_SNOC_GEM_NOC_GC 551
|
||||
#define SLAVE_SNOC_GEM_NOC_SF 552
|
||||
#define SLAVE_LLCC 553
|
||||
#define SLAVE_LPASS_GEM_NOC 554
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 555
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 556
|
||||
#define SLAVE_CDSP_MEM_NOC 557
|
||||
#define SLAVE_MEM_NOC_PCIE_SNOC 558
|
||||
#define SLAVE_ANOC_PCIE_GEM_NOC 559
|
||||
#define SLAVE_APPSS 560
|
||||
#define SLAVE_CNOC_CFG 561
|
||||
#define SLAVE_DDRSS_CFG 562
|
||||
#define SLAVE_CNOC_MNOC_HF_CFG 563
|
||||
#define SLAVE_CNOC_MNOC_SF_CFG 564
|
||||
#define SLAVE_NSP_QTB_CFG 565
|
||||
#define SLAVE_PCIE_ANOC_CFG 566
|
||||
#define SLAVE_WLAN_Q6_THROTTLE_CFG 567
|
||||
#define SLAVE_QUP_CORE_0 568
|
||||
#define SLAVE_QUP_CORE_1 569
|
||||
#define SLAVE_IMEM 570
|
||||
#define SLAVE_PIMEM 571
|
||||
#define SLAVE_SERVICE_CNOC_CFG 572
|
||||
#define SLAVE_SERVICE_CNOC 573
|
||||
#define SLAVE_SERVICE_MNOC_HF 574
|
||||
#define SLAVE_SERVICE_MNOC_SF 575
|
||||
#define SLAVE_SERVICE_PCIE_ANOC 576
|
||||
#define SLAVE_PCIE_0 577
|
||||
#define SLAVE_PCIE_1 578
|
||||
#define SLAVE_QDSS_STM 579
|
||||
#define SLAVE_TCU 580
|
||||
#define MASTER_LLCC_DISP 1000
|
||||
#define MASTER_MDP_DISP 1001
|
||||
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
|
||||
|
||||
Loading…
Reference in New Issue
Block a user