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Merge "clk: qcom: debugcc-niobe: Add gx clocks measure_only support"

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qctecmdr 2024-04-24 02:55:53 -07:00 committed by Gerrit - the friendly Code Review server
commit f6a7b61c5f
1 changed files with 66 additions and 2 deletions
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68
drivers/clk/qcom/debugcc-niobe.c
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@ -841,7 +841,6 @@ static const char *const gpu_cc_debug_mux_parent_names[] = {
"gpu_cc_cx_ff_clk",
"gpu_cc_cx_gmu_clk",
"gpu_cc_cxo_clk",
"gpu_cc_demet_clk",
"gpu_cc_freq_measure_clk",
"gpu_cc_gx_accu_shift_clk",
"gpu_cc_gx_acd_ahb_ff_clk",
@ -853,6 +852,7 @@ static const char *const gpu_cc_debug_mux_parent_names[] = {
"gx_clkctl_debug_mux",
"measure_only_gpu_cc_cb_clk",
"measure_only_gpu_cc_cxo_aon_clk",
"measure_only_gpu_cc_demet_clk",
"measure_only_gpu_cc_gx_ahb_ff_clk",
"measure_only_gpu_cc_rscc_hub_aon_clk",
"measure_only_gpu_cc_rscc_xo_aon_clk",
@ -865,7 +865,6 @@ static int gpu_cc_debug_mux_sels[] = {
0x20, /* gpu_cc_cx_ff_clk */
0x1D, /* gpu_cc_cx_gmu_clk */
0x1E, /* gpu_cc_cxo_clk */
0x10, /* gpu_cc_demet_clk */
0xF, /* gpu_cc_freq_measure_clk */
0x15, /* gpu_cc_gx_accu_shift_clk */
0x13, /* gpu_cc_gx_acd_ahb_ff_clk */
@ -877,6 +876,7 @@ static int gpu_cc_debug_mux_sels[] = {
0xB, /* gx_clkctl_debug_mux */
0x28, /* measure_only_gpu_cc_cb_clk */
0xE, /* measure_only_gpu_cc_cxo_aon_clk */
0x10, /* measure_only_gpu_cc_demet_clk */
0x12, /* measure_only_gpu_cc_gx_ahb_ff_clk */
0x29, /* measure_only_gpu_cc_rscc_hub_aon_clk */
0xD, /* measure_only_gpu_cc_rscc_xo_aon_clk */
@ -904,11 +904,21 @@ static struct clk_debug_mux gpu_cc_debug_mux = {
};
static const char *const gx_clkctl_debug_mux_parent_names[] = {
"measure_only_acd_gfx3d_clk",
"measure_only_gx_accu_clk",
"measure_only_gx_clkctl_demet_clk",
"measure_only_gx_gfx3d_clk",
"measure_only_gx_gfx3d_rdvm_clk",
"measure_only_mnd1x_gfx3d_clk",
};
static int gx_clkctl_debug_mux_sels[] = {
0x8, /* measure_only_acd_gfx3d_clk */
0xA, /* measure_only_gx_accu_clk */
0x2, /* measure_only_gx_clkctl_demet_clk */
0x3, /* measure_only_gx_gfx3d_clk */
0x6, /* measure_only_gx_gfx3d_rdvm_clk */
0x7, /* measure_only_mnd1x_gfx3d_clk */
};
static struct clk_debug_mux gx_clkctl_debug_mux = {
@ -1005,6 +1015,14 @@ static struct mux_regmap_names mux_list[] = {
{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
};
static struct clk_dummy measure_only_acd_gfx3d_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_acd_gfx3d_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_apcs_gold_post_acd_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
@ -1189,6 +1207,14 @@ static struct clk_dummy measure_only_gpu_cc_cxo_aon_clk = {
},
};
static struct clk_dummy measure_only_gpu_cc_demet_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_gpu_cc_demet_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_gpu_cc_gx_ahb_ff_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
@ -1221,6 +1247,22 @@ static struct clk_dummy measure_only_gpu_cc_sleep_clk = {
},
};
static struct clk_dummy measure_only_gx_accu_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_gx_accu_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_gx_clkctl_demet_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_gx_clkctl_demet_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_gx_gfx3d_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
@ -1229,6 +1271,14 @@ static struct clk_dummy measure_only_gx_gfx3d_clk = {
},
};
static struct clk_dummy measure_only_gx_gfx3d_rdvm_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_gx_gfx3d_rdvm_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_ipa_2x_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
@ -1285,6 +1335,14 @@ static struct clk_dummy measure_only_memnoc_clk = {
},
};
static struct clk_dummy measure_only_mnd1x_gfx3d_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
.name = "measure_only_mnd1x_gfx3d_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_dummy measure_only_pcie_0_pipe_clk = {
.rrate = 1000,
.hw.init = &(const struct clk_init_data){
@ -1398,6 +1456,7 @@ static struct clk_dummy measure_only_video_cc_xo_clk = {
};
static struct clk_hw *debugcc_niobe_hws[] = {
&measure_only_acd_gfx3d_clk.hw,
&measure_only_apcs_gold_post_acd_clk.hw,
&measure_only_apcs_gold_pre_acd_clk.hw,
&measure_only_apcs_goldplus_post_acd_clk.hw,
@ -1421,11 +1480,15 @@ static struct clk_hw *debugcc_niobe_hws[] = {
&measure_only_gcc_video_xo_clk.hw,
&measure_only_gpu_cc_cb_clk.hw,
&measure_only_gpu_cc_cxo_aon_clk.hw,
&measure_only_gpu_cc_demet_clk.hw,
&measure_only_gpu_cc_gx_ahb_ff_clk.hw,
&measure_only_gpu_cc_rscc_hub_aon_clk.hw,
&measure_only_gpu_cc_rscc_xo_aon_clk.hw,
&measure_only_gpu_cc_sleep_clk.hw,
&measure_only_gx_accu_clk.hw,
&measure_only_gx_clkctl_demet_clk.hw,
&measure_only_gx_gfx3d_clk.hw,
&measure_only_gx_gfx3d_rdvm_clk.hw,
&measure_only_ipa_2x_clk.hw,
&measure_only_mccc_clk.hw,
&measure_only_mdss_0_disp_cc_sleep_clk.hw,
@ -1433,6 +1496,7 @@ static struct clk_hw *debugcc_niobe_hws[] = {
&measure_only_mdss_1_disp_cc_sleep_clk.hw,
&measure_only_mdss_1_disp_cc_xo_clk.hw,
&measure_only_memnoc_clk.hw,
&measure_only_mnd1x_gfx3d_clk.hw,
&measure_only_pcie_0_pipe_clk.hw,
&measure_only_pcie_1_phy_aux_clk.hw,
&measure_only_pcie_1_pipe_clk.hw,