Add 2.5G support for SA8775 and enable CL45 read write
through indirect read/write APIs.
Change-Id: Ia71501f27429ff775a1b39a6754922047d30a44f
Signed-off-by: Srinath Pandey <quic_srinpand@quicinc.com>
Add support to detect higher thermal profile parts and update thermal
zone trips dynamically based on nvmem cell data for tsens.
Change-Id: I792c4f2736d10d68b45cc9b64c0ec08d185cf007
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
During ranging sessions back to back doorbells from SOC racing with
UWB session request and multi CRs reported and sma_wr_pending not set
if the doorbell has independent doorbell. After that if we get another
independent doorbell we could see the failure for processing independent
doorbell becz sma write was pending part of previous multi CR.
Change-Id: I6b8cfa86f80038935877360896f383084fbb04c1
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
There is function prototype mismatch in tsens init function.
Enable __init keyword only for static driver case.
Fix issues in clean up also in init function.
Change-Id: Id7eaf4c65e78c1864c8b377ed0137c45cce256ad
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
First stage module like tsens depends on qfprom module.
Enable it in first stage DLKMs list.
Change-Id: Id38b3a66f174c77b80dd6f020d1eca706955bb7e
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
Currently, if APPS sends more than 10 requests to RPM, glink
hard interrupt service function is unable to process more than 10
acknowledgements.
Increase the loop iterations to 15 to process up to 15 acknowledgements
in the hard interrupt context.
Change-Id: Ief7385f21d5853275a2b90438181c93a01c76f78
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
In the host mode suspend scenario, the dwc3 core executes
dwc3_core_exit, which suspends the USB PHYs and turn off the clocks.
Later, during the dwc3-msm PM suspend, it invokes notify_disconnect to
the PHYs. As part of the SS PHY disconnect, it attempts to power down,
leading to a NOC error. To address this, a check has been added to
enable the clock during the power-down process.
Change-Id: I6040c431dea4a693a7226dc3006c099eb43bce43
Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
Add pwm reset support so that for each frame, period and
duty_cycle can be changed dynamically. While at it, also
update the pdm_pwm_free API with PWM disable functionality.
Change-Id: I64ecd4a8cec948d56cb89e7a5ae4b30e70cb9f3e
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
TCSR_SOCCP_SLEEP_STATUS is updated when SOCCP starts wakeup process
and is not done processing the sleep request, Check the D0 state
transition by polling on SOCCP_SPARE register.
Change-Id: I7a00ec58f99ca748857e93ce4aab5a8dcc126faf
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Signed-off-by: Kamati Srinivas <quic_kamasrin@quicinc.com>
Clear the master kernel bit if the SOCCP does not honour the
APPS request for a state change.
Change-Id: I5a6747973ed87e4c7f0d9074ef8da56925d2a927
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Signed-off-by: Kamati Srinivas <quic_kamasrin@quicinc.com>
This reverts commit a8ce5c2552.
TCSR register read can be solely relied upon for D0 confirmation.
Change-Id: I9cb11a13313d2a9964efdc02a77b698b62268070
Signed-off-by: Kamati Srinivas <quic_kamasrin@quicinc.com>
When Slave receives sleep command from host it requires 1msec to handle
the sleep due to HW limitation. Host should wait some time >1ms after
sending sleep command and before initiating next command to slave.
Added changes to check for slave_sleep_lock and wait for 2msec to
initiate transfers from host post sleep command.
Change-Id: Id333e2acecdb0ab169565f343b27d61952fb9471
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Keeping enable GPIO always high leads to higher power consumption,
even in RBSC, when the regulator is not in use. Toggle GPIO to high
state only when regulator is enabled and toggle it low after regulator
disable to avoid power consumption when the regulator is not in use.
Change-Id: Ic2f9c0ef350051776f094e55e6fb4967b0d45248
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Enable the interconnect driver so that consumers are
able to obtain their path handles properly.
Change-Id: Iaddfe9f00152d68a8ed2ee655df487ded0c2a5c0
Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
Add tcsrcc and gdsc-regulator modules to modules list on NEO platform,
to enable it to load during first stage init.
Change-Id: I8feb175c570abbc3e0a458615f2d1f08e0444f71
Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
Add support for seraph pin configuration and control
in pinctrl framework.
Change-Id: I0673e080925601ba53f142279258d79af33d3aac
Signed-off-by: Navya Vemula <quic_nvemula@quicinc.com>
Currently bootloader does the following to calculate the authentication
tag slot number.
authslot = NrMetaPages + NrCopyPages + NrSwapMapPages +
HDR_SWP_INFO_NUM_PAGES
However, with compression enabled, we cannot apply the above logic to
get the authentication slot number. So this data should be provided to
the bootloader for decryption to work.
The current implementation doesn't make use of the swap_map_pages
for restoring the hibernation image. Use the slot number of the first
swap_map_page to store the authentication tag slot number.
Change-Id: Iddfb98cc5adc7bd79c0f52f3f5d64ad282efc9b4
Signed-off-by: Nikhil V <quic_nprakash@quicinc.com>
In case of hibernation with compression enabled, 'n' number of pages
will be compressed to 'x' number of pages before being written to the
disk. Keep a note of these compressed block counts so that bootloader
can directly read 'x' pages and pass it on to the decompressor. An
array will be maintained which will hold the count of these compressed
blocks and later on written to the disk as part of the hibernation
image save process.
Change-Id: If48cd5c396eda674467b3d40c75ad3c2e91c2e5e
Signed-off-by: Nikhil V <quic_nprakash@quicinc.com>
