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net: ethernet: stmmac: Add 2.5G Phy Support

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Add 2.5G support for SA8775 and enable CL45 read write
through indirect read/write APIs.

Change-Id: Ia71501f27429ff775a1b39a6754922047d30a44f
Signed-off-by: Srinath Pandey <quic_srinpand@quicinc.com>
This commit is contained in:
Srinath Pandey 2024-08-19 01:32:22 +05:30
parent 7bf59b2974
commit fef9e81ee1
4 changed files with 17 additions and 5 deletions
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7
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
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@ -2832,5 +2832,12 @@ module_init(qcom_ethqos_init_module)
module_exit(qcom_ethqos_exit_module)
#if IS_ENABLED(CONFIG_AQUANTIA_PHY)
MODULE_SOFTDEP("post: aquantia");
#endif
#if IS_ENABLED(CONFIG_MARVELL_PHY)
MODULE_SOFTDEP("post: marvell");
#endif
MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
MODULE_LICENSE("GPL v2");

4
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
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@ -380,8 +380,8 @@ static int dwmac4_get_hw_feature(void __iomem *ioaddr,
dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
// dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
dma_cap->sphen = 0;
dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
switch (dma_cap->addr64) {
case 0:

2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
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@ -7479,6 +7479,8 @@ int stmmac_dvr_probe(struct device *device,
ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
#ifdef STMMAC_VLAN_TAG_USED
ndev->vlan_features |= ndev->hw_features;
priv->dma_cap.vlhash = 0;
priv->dma_cap.vlins = 0;
/* Both mac100 and gmac support receive VLAN tag detection */
ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
priv->dma_cap.vlhash = 0;

9
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
View File

@ -506,9 +506,12 @@ int stmmac_mdio_register(struct net_device *ndev)
} else {
err = new_bus->read(new_bus, phyaddr, MII_BMSR);
if (err == -EBUSY || !err || err == 0xffff) {
dev_warn(dev, "Invalid PHY address read from dtsi: %d\n",
phyaddr);
new_bus->phy_mask = mdio_bus_data->phy_mask;
err = of_property_read_u32(np, "emac-cl45-phy-addr", &phyaddr);
new_bus->phy_mask = ~(1 << phyaddr);
skip_phy_detect = 1;
new_bus->read = &virtio_mdio_read_c45_indirect;
new_bus->write = &virtio_mdio_write_c45_indirect;
new_bus->probe_capabilities = MDIOBUS_C22_C45;
} else {
new_bus->phy_mask = ~(1 << phyaddr);
skip_phy_detect = 1;