Commit Graph

1006307 Commits

Author SHA1 Message Date
qctecmdr
043f4ebf83 Merge "msm: ep-pcie: Correct two CAP reg offsets" 2021-11-22 23:49:45 -08:00
qctecmdr
a44c4e5906 Merge "msm: ep-pcie: Allow device enter L1 right after BME is set" 2021-11-22 23:49:44 -08:00
qctecmdr
dc94aa7b5d Merge "msm: ep_pcie: Correct clkreq override value" 2021-11-22 23:49:43 -08:00
qctecmdr
fa36433f45 Merge "sched/walt: Improve the scheduler" 2021-11-22 21:38:44 -08:00
Siva Kumar Akkireddi
d8f9f29196 msm: ep_pcie: Correct clkreq override value
Use unshifted value to set the clock req override value
and enable fields as the register write function already
shifts the values to the correct position.

Change-Id: I0b5dea0f6f8462363471910ffe93f8f8975e7929
Signed-off-by: Siva Kumar Akkireddi <sivaa@codeaurora.org>
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
2021-11-23 10:56:07 +05:30
Can Guo
18afbf4da4 msm: ep-pcie: Correct two CAP reg offsets
Correct the offsets of L1SUB_CAPABILITY_REG and L1SUB_CONTROL1_REG.

Change-Id: I6130a7eab50d85e34d87c28bde3a48c058ee9eee
Signed-off-by: Can Guo <cang@codeaurora.org>
2021-11-23 10:43:56 +05:30
Can Guo
0aae96cfb3 msm: ep-pcie: Allow device enter L1 right after BME is set
Allow device enter L1, i.e. clear PCIE_0_PCIE_PARF_PM_CTRL[REQ_NOT_ENTR_L1]
once we find out BME is set.

Change-Id: I8aca816446a286d02ef51724d157cb7c75057250
Signed-off-by: Can Guo <cang@codeaurora.org>
2021-11-22 20:51:50 -08:00
qctecmdr
9eb990d0a9 Merge "net: qrtr: gunyah: Cleanup gh_rm_mem_qcom_lookup_sgl calls" 2021-11-22 17:29:13 -08:00
Stephen Dickey
17ebcaf0a8 sched/walt: Improve the scheduler
This change is for general scheduler improvement.

Change-Id: Id758a4a0a836fe30b9f63b8f00c017247cf3b84c
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
2021-11-22 17:13:13 -08:00
qctecmdr
f553034de9 Merge "msm: kgsl: Add new tracepoints for command batch ready and done" 2021-11-22 09:26:54 -08:00
qctecmdr
c5893d6b33 Merge "msm: kgsl: Remove RBBM_GPC_ERROR from a6xx hwsched interrupt mask" 2021-11-22 09:26:53 -08:00
qctecmdr
085b994fc4 Merge "msm: mhi: Handle PCIe events from the common work queue" 2021-11-22 07:25:29 -08:00
qctecmdr
b42c4b3244 Merge "defconfig: Enable additional configs for compilation" 2021-11-22 05:15:02 -08:00
qctecmdr
a6925a8815 Merge "cpufreq: qcom-hw: switch to non deferrable work" 2021-11-19 17:17:14 -08:00
Patrick Daly
0b4dfc4dfe net: qrtr: gunyah: Cleanup gh_rm_mem_qcom_lookup_sgl calls
Recent hypervisor images no longer support gh_rm_mem_qcom_lookup_sgl().
Remove this to cleanup associated error messages in the log.

Change-Id: I01cd80cb5dc199f778a7ad44fa2a3cfa5f56a31f
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
2021-11-19 15:48:34 -08:00
qctecmdr
0417b3811c Merge "msm: kgsl: Enable bus voting on minimal powerlevel" 2021-11-19 15:19:12 -08:00
qctecmdr
f62fb0701c Merge "remoteproc: qcom: Do not Panic if there is no vote on rproc" 2021-11-19 13:24:48 -08:00
Oleg Perelet
7da359c615 msm: kgsl: Enable bus voting on minimal powerlevel
There are usecases where GPU is not busy but GPU consumes high ddr
bandwidth. In such case, bus DCVS will not kick in, potentially causing
an under voting scenario. Enable bus voting on minimal power level, even
if GPU busy is less than 75%.

Change-Id: I02db2e4b68ce9d48c2f755112f0dcf9912936b56
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
2021-11-19 10:36:00 -08:00
qctecmdr
4be7c16fe9 Merge "msm: mhi-dev: Flush ereqs from dev close to avoid OOS transfers" 2021-11-19 09:08:32 -08:00
qctecmdr
607a15511b Merge "msm: mhi_dev: Handle potential deadlock situation" 2021-11-19 09:08:31 -08:00
qctecmdr
48df15b6c9 Merge "msm: mhi_dev: Serialize UCI open and close file node operations" 2021-11-19 07:21:33 -08:00
qctecmdr
76e90fa255 Merge "defconfig: Enable additional configs for compilation" 2021-11-19 07:21:31 -08:00
qctecmdr
d7879bfe0b Merge "msm: ep-pcie: Fix icc bus vote and add icc bus unvote" 2021-11-19 07:21:31 -08:00
qctecmdr
85fb1fa329 Merge "icnss2: Ignore ramdump device failure error" 2021-11-19 07:21:30 -08:00
Mukesh Ojha
bbe873dee9 remoteproc: qcom: Do not Panic if there is no vote on rproc
There is no point of panic and collect ramdump if there is
no power vote for the subsystem, it is as good subsystem is
down and memory is cleaned.

Change-Id: Ia5f55e756409a26830c70b80828dab0ef673f1bb
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
2021-11-19 19:34:19 +05:30
qctecmdr
f5cebbb404 Merge "scsi: ufs-qcom: configure ufs clocks core memory" 2021-11-19 05:21:34 -08:00
qctecmdr
f071855366 Merge "soc: qcom: mem-offline: timeout mechanism for memory offline" 2021-11-19 05:21:34 -08:00
qctecmdr
9551ae8f2a Merge "msm: mhi: Queue pending_ring WQ post channel DB check" 2021-11-19 05:21:33 -08:00
qctecmdr
c02a77a5ae Merge "msm: mhi_dev: check for error during ring processing" 2021-11-19 05:21:32 -08:00
qctecmdr
39e1e20d6c Merge "msm: mhi_dev: Ensure the flush list is empty for a stopped channel" 2021-11-19 05:21:31 -08:00
qctecmdr
b1b618e1ab Merge "msm: mhi_dev: Check to prevent in_use_list access" 2021-11-19 05:21:31 -08:00
qctecmdr
3e514b3bc9 Merge "Merge keystone/android12-5.10-keystone-qcom-release.66+ (611d258) into msm-5.10" 2021-11-19 00:18:23 -08:00
Naman Padhiar
9422d0ee6b icnss2: Ignore ramdump device failure error
Register remote proc framework even ramdump device
create gets fail.

Change-Id: Iff8047667be6751f5ca7ef89e69c5c9558cec538
Signed-off-by: Naman Padhiar <quic_npadhiar@quicinc.com>
2021-11-19 13:44:12 +05:30
Nitesh Gupta
d491e8d909 msm: mhi_dev: Handle potential deadlock situation
With the current logic, MHI driver will hold channel
lock while processing the ring element and triggers
callback for the clients. Some clients are issuing
read requests for the channel in the callback context.
MHI driver will try to acquire the same channel lock
in read api leading to a deadlock situation.

Modify the logic to avoid holding channel lock
while processing the ring elements.

Change-Id: I62ac28d5eb06e3c9b12437f02288cfe1cdb2bea2
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-19 13:00:57 +05:30
Subramanian Ananthanarayanan
9a6e61c425 msm: mhi_dev: Check to prevent in_use_list access
Added a check for accessing in_use_list only in async case.

Change-Id: I842f9b9feb688d75152f7b2639c17c25c3376236
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-18 23:29:28 -08:00
Hareesh Gundu
0fad62f7da msm: kgsl: Remove RBBM_GPC_ERROR from a6xx hwsched interrupt mask
RBBM_GPC interrupt is handled by GMU for hwsched enabled targets.
Hence remove this from the a6xx hwsched interrupt mask.

Change-Id: I7cc409514a59e528fa8310640197c1743a9d201d
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
2021-11-19 12:58:36 +05:30
Subramanian Ananthanarayanan
029cf97f28 msm: mhi_dev: Use req_lock spinlock during client release
The change is to use req_lock spinlock during client release
and to use the same spinlock while checking for is_stale
during read/write completion callbacks.

Change-Id: I7ebafecb7503fa8521fa8f849cabf4b82bbc2f53
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-19 12:53:40 +05:30
Subramanian Ananthanarayanan
df2f032c5f msm: mhi_dev: Serialize UCI open and close file node operations
Multiple clients might perform open and close file operations
simultaneously on the same file node created by UCI. To avoid
race conditions which might result in invalid accesses or crashes,
the open and close operations are serialized.

Change-Id: Ic6a290a2c6af25bcd60983a7b531bf1287201821
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-18 23:19:15 -08:00
qctecmdr
896e302db9 Merge "msm: mhi_dev: free allocated memory in reverse order of allocation" 2021-11-18 22:21:29 -08:00
qctecmdr
8363ec830f Merge "cnss2: Update kernel service files for new features" 2021-11-18 22:21:28 -08:00
Veerabhadrarao Badiganti
43bbd74eb9 msm: mhi_dev: Ensure the flush list is empty for a stopped channel
If a channel gets stopped, while there are some outstanding requests/
transfers with IPA, then we simply ignore the completion from IPA.
But we must have already added the transfer-completion-event to the
flush list before submitting the transfer to IPA.

There is a possibility that we flush these stale events along with new
flush events (for new requests) when the channel gets re-started.
This un-intentional completion event can lead to out-of-sequence
events at the host.

So while stopping a channel, ensure all elements in the flush list
of that channel are discarded and the flush list is empty.

Change-Id: I04445b1f9f4d2d4fce0b8a96277517de14481ead
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
2021-11-19 10:45:05 +05:30
Gauri Joshi
40821f01e9 msm: mhi-dev: Flush ereqs from dev close to avoid OOS transfers
Currently there is a race condition where during the flushing of ereqs
the channel is closed from the client on the EP side, which is causing
the flush function to access null memory. To avoid that call the flush
from dev close which ensures all the pending ereqs are closed before
closing the channel and freeing the memory.

Change-Id: Id81d8cb8b326340d28f6cfe9d48dcd685a8038f9
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-19 10:40:58 +05:30
Subramanian Ananthanarayanan
d697c9681a msm: mhi_dev: check for error during ring processing
The change is to check for error code from cmd processing in case
of db pending cases, to avoid rd_offset increment.

Change-Id: If213297fe02ec1087bfab572f5af97b1e7bb5791
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-11-19 10:22:34 +05:30
Veerabhadrarao Badiganti
950e975129 scsi: ufs-qcom: configure ufs clocks core memory
Configure the ufs clocks core and peripheral memory state when
turned off. This configuration is required to allow retaining
ICE crypto configuration (including keys) when ice_core_clk is
turned off, and powering down non-ICE RAMs of host controller.

Change-Id: I93584851fd50c7006ccd48979087d707ab4c6408
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[vbadigan@codeaurora.org: updated clk_set_flag API with new API]
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
2021-11-18 20:24:16 -08:00
qctecmdr
5361cb67a5 Merge "Revert "locking/rwsem: Add vendor hook for rwsem enhancement"" 2021-11-18 20:21:53 -08:00
qctecmdr
f1de19f142 Merge "msm: mhi-dev: Check to avoid null pointer dereference" 2021-11-18 18:33:10 -08:00
qctecmdr
f217503166 Merge "drivers: firmware: pmu_vendor: add cmd to enable tracing" 2021-11-18 16:32:56 -08:00
qctecmdr
16affeb5a6 Merge "msm: mhi: Prevent flush queue if channel is closed" 2021-11-18 14:26:42 -08:00
qctecmdr
6373aa8774 Merge "msm: kgsl: Remove undefined HLSQ register dump to A6xx snapshot" 2021-11-18 12:29:25 -08:00
qctecmdr
91b728213a Merge "usb: repeater: Add eUSB2 repeater driver" 2021-11-18 12:29:25 -08:00