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msm: ep-pcie: Allow device enter L1 right after BME is set

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Allow device enter L1, i.e. clear PCIE_0_PCIE_PARF_PM_CTRL[REQ_NOT_ENTR_L1]
once we find out BME is set.

Change-Id: I8aca816446a286d02ef51724d157cb7c75057250
Signed-off-by: Can Guo <cang@codeaurora.org>
This commit is contained in:
Can Guo 2021-05-12 07:59:17 +08:00 committed by Gerrit - the friendly Code Review server
parent 9eb990d0a9
commit 0aae96cfb3
1 changed files with 9 additions and 4 deletions
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13
drivers/platform/msm/ep_pcie/ep_pcie_core.c
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@ -659,10 +659,6 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
PCIE20_LINK_CONTROL2_LINK_STATUS2,
0xf, dev->link_speed);
EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",
dev->rev);
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",
dev->rev);
if (!dev->tcsr_not_supported) {
@ -1982,6 +1978,11 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
dev->rev, retries,
BME_TIMEOUT_US_MIN * retries / 1000);
ep_pcie_enumeration_complete(dev);
EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",
dev->rev);
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
/* expose BAR to user space to identify modem */
ep_pcie_bar0_address =
readl_relaxed(dev->dm_core + PCIE20_BAR0);
@ -2157,6 +2158,10 @@ static irqreturn_t ep_pcie_handle_bme_irq(int irq, void *data)
dev->rev);
ep_pcie_notify_event(dev, EP_PCIE_EVENT_LINKUP);
}
EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",
dev->rev);
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
} else {
EP_PCIE_DBG(dev,
"PCIe V%d:BME is still disabled\n", dev->rev);