Enable the following modules which enables
data encryption (FBE) using wrapped keys.
CONFIG_QTI_CRYPTO_COMMON
CONFIG_SCSI_UFS_CRYPTO_QTI.
Change-Id: I4bbd01f3f559be6cc8a82d011938cb7684b08919
Signed-off-by: Akhil Budampati <quic_abudampa@quicinc.com>
Add core support and virt-wdog in firststage.
Change-Id: If764fef0ee0785a63b7018b9819c156cebefeb59
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Enable watchdog and related configs for pitti SoC.
Change-Id: Ic6307941495078416efa5036953f4325b0dbcdf6
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Enable SCSI Generic Kernel Module support for Pitti
to enable communication from kernel for underlying
storage devices using the SCSI protocol.
Change-Id: Ibb80ae11692e2fbf16172dba1759e33d20a1f89f
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
In the latest builds, the dwc3_gadget_init_in/out_endpoint functions
seem to be inline. Modify msm ops to use usb_ep_set_maxpacket_limit
call to set this ep limit to 1024 for non-zero endpoints.
Change-Id: Ic1c965b85a5a3fb7cf4fafb3dc4273fd6f29e729
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
wcd_usbss is not support on pitti, so remove.
Change-Id: I1a0648fd5a5c55bab03ed14d8e81e266996f26d5
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
The perf_mode flag doesn't exist upstream yet, so the new
bcm_aggregate_mask() brought in from the LTS merge doesn't handle it.
Add back the perf_mode support.
Change-Id: I27d03ceceb55816c1d26735c8b3713fc32bbd9c2
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Enable the fastmap, ECATS debug, TLB sync timeout debug and
iommu logger features through related configs for pitti.
Change-Id: Ie854215fb42754500bc1e4f7cc54d5b8f0fc140c
Signed-off-by: Jaskaran Singh <quic_jasksing@quicinc.com>
Move XO clock in phy driver to remove the dependency on
dwc3 glue driver. Add the votes required for phy to
be operational using the optional ref_clk.
Change-Id: Ieb081ad1bbf9a00c4029ae9abdc1c58eaff81462
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
Some devices are slow in responding to Control transfers. Scheduling
multiple transactions in one microframe/frame can cause these devices
to misbehave.
This change enables Sparse Control transaction so that the host
controller schedules each phase of a Control transfer in different
microframes/frames.
Change-Id: I6b1320d980852e6d85b0bb39fd566d6fdfaa54e9
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
The SoC Control Processor (SoCCPP) is small RISCV subsystem providing
support for general SoC infrastructure management that cannot be
effectively managed by the CPU or larger DSPs. It provides a solution
for control-plane processing, reducing per-subsystem microcontroller
reinvention.
SoCCP driver borrows the unprepare/start/stop/load/coredump callback
from the pas client driver and in addition adds an API (rproc_set_state),
this API is exposed to the SoCCP client drivers to control the power
modes of SoCCP. The power modes controlled by the clients are dormant
and active.
rproc_set_state is refcounted and the request to set to dormant state
is sent to SoCCP only if there are no active clients for SoCCP.
set_state_soccp is blocking API which polls on the config register for
the requested state change.
Change-Id: I7e2bf5e7c13afdb849a8008985a33b7d0f9b321a
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Signed-off-by: Kamati Srinivas <quic_kamasrin@quicinc.com>
This change will enable system suspend and resume support
in q2spi interface driver and allow the
device to enter low power modes.
Change-Id: I7d936fe3f9236c41f58907e34bf3e0a6b37e9432
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
As part of 'commit 8519591b50
("q2spi-msm-geni: Fix memory leaks")' cr packet is
freed in q2spi_process_hrf_flow_after_lra which is
being accessed later in doorbell_work handler
resulting in use after free access.
Prevent the crash by not freeing cr packet in
q2spi_process_hrf_flow_after_lra.
Change-Id: I5051e95991ef59dc824b9299c94edf19b0a1ae21
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
This change will add separate gsi rx callback function for
doorbell. Also added changes to serialise the mapping of
rx dma buffer for independent doorbell data from ganges first
and then map the rx dma buffer for next doorbell.
Change-Id: Ic4431d82ed17a0b2e764d8c374b54d4c86f0c6d3
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Currently during system shutdown, power down command
is sent to ufs subsystem. After this we put all the
UFS rails in low power modes immediately but it seems
some ufs devices may still draw more than sleep current
from UFS rails (especially from VCCQ rail) at least for
some micro seconds. It causes OCP on VCCQ rail.
Hence avoid turning off UFS VCCQ regulator in ufs
shutdown by putting an additional vote on VCCQ
LDO if 'qcom,vccq-shutdown' is defined in target
DTS. UFS device LDO would be turned off by PMIC
regulator itself.
Change-Id: Ibf5764152e9460a0dc96ec121345920c06b985a5
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Memory dump and DCC modules need to be loaded at first stage to
setup the memory dump table and DCC link list early during boot
up.
Change-Id: Id5d4258ef7c8dafab218aac430aaf867546cfe6d
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
USB QDSS function driver is needed for axcercizing the usecases of
QDSS choosing USB and sink and dump the tracing directly to host PC.
The following defconfig enbled the function driver responsible for
acting as the transport layer. Also add it to the bzl file.
Change-Id: I353ded8bd50486c83147b87d5f0883a037181b21
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
Add the register offset pair of USB3-DP phy for pitti.
Change-Id: Ia2a261fb88e6fb17fc772902f3fc17f5dbbc9ec7
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Add support for gpu scan dump skip cooling device driver. This
driver will register with thermal framework as a cooling device.
This driver will enable the feature to update a PMIC SDAM and a
SOC cookie which will be checked in SDI path to disable GFX rail
and skip GPU Scan dump when ambient temperature is more than the
recommended threshold.
Change-Id: I8976a150e61254d98063ec9d5eabbfe733009fc6
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
Change the apss_ahb_clk_src rate to 19.2MHz during probe and enable the
RCG to keep it always on. Also change parent from gcc_xo_gpll0 to
gcc_xo_gpll0_ao for preventing XO shutdown issues. Update the frequency
table by removing unneeded frequencies.
Change-Id: Ia96f907c8d1dc2dea2765116625a92944f5d66b8
Signed-off-by: Khushal Bawankar <quic_kbawanka@quicinc.com>
Signed-off-by: Shubham Diwane <quic_sanantad@quicinc.com>
