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clk: qcom: gcc-mdm9607: Update apss_ahb_clk_src freq table and parent

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Change the apss_ahb_clk_src rate to 19.2MHz during probe and enable the
RCG to keep it always on. Also change parent from gcc_xo_gpll0 to
gcc_xo_gpll0_ao for preventing XO shutdown issues. Update the frequency
table by removing unneeded frequencies.

Change-Id: Ia96f907c8d1dc2dea2765116625a92944f5d66b8
Signed-off-by: Khushal Bawankar <quic_kbawanka@quicinc.com>
Signed-off-by: Shubham Diwane <quic_sanantad@quicinc.com>
This commit is contained in:
Khushal Bawankar 2023-09-12 11:48:29 +05:30 committed by Shubham Ananta Diwane
parent 50606fe973
commit 7c539936f9
1 changed files with 14 additions and 5 deletions
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19
drivers/clk/qcom/gcc-mdm9607.c
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@ -4,6 +4,7 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
@ -105,6 +106,11 @@ static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .hw = &gpll0.clkr.hw },
};
static const struct clk_parent_data gcc_xo_gpll0_ao[] = {
{ .fw_name = "xo_ao" },
{ .hw = &gpll0.clkr.hw },
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
@ -228,8 +234,6 @@ static const struct clk_parent_data gcc_xo_emac_0_125m[] = {
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
@ -240,10 +244,9 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.freq_tbl = ftbl_apss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.parent_data = gcc_xo_gpll0_ao,
.num_parents = 2,
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
@ -1997,6 +2000,7 @@ MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table);
static int gcc_mdm9607_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
if (IS_ERR(vdd_dig.regulator[0])) {
@ -2013,7 +2017,12 @@ static int gcc_mdm9607_probe(struct platform_device *pdev)
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
ret = qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
clk_set_rate(apss_ahb_clk_src.clkr.hw.clk, 19200000);
clk_prepare_enable(apss_ahb_clk_src.clkr.hw.clk);
return ret;
}
static struct platform_driver gcc_mdm9607_driver = {