Currently, the avb_boot_img rule uses "openssl" from the host while
building. This causes a build error on hosts that do not have openssl
installed.
Since openssl is included in the prebuilt hermetic tools, let's update
the rule to use those instead.
Change-Id: Iddd95a3a74690bfe5e94733e810eed8800e77c39
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
This reverts commit 04816e672d.
Avoid modification of dll_config_3 register based on the clock freq.
For EMMC if clock freq is greater than 150Mhz then
the existing logic will modify it to 0x10 whereas expected is 0x01.
And hence results in dll mismatch.
Change-Id: Ibdee59c3c5057c1434a234ad1548d09ae96dd05a
Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com>
Add smmu enablement and smmu mapping for ethernet and
add support for Micrel PHY interrupt.
Change-Id: Ia7cf0847cc930f8ea3b54b8474f0b7b6f907b479
Signed-off-by: Sarosh Hasan <quic_sarohasa@quicinc.com>
During PM suspend, due to lack of proper prepare/complete PM
callbacks in the device chain, the direct_complete parameter used to
skip the PM suspend/resume callbacks for the DWC3 core device. During
hibernation, direct_complete parameter is set to false and hence
dwc3 PM resume is being called during thaw operation, while dwc3 msm
is not PM resumed. This results in accessing registers which leads
unclocked access. Fix it by marking dwc3 core device as syscore device
to skip dwc3 PM suspend/resume during hibernation entry/exit.
Change-Id: I8b8b8cd28f4a323b989745553ec3fce75209ecaf
Signed-off-by: Vijayavardhan Vennapusa <quic_vvreddy@quicinc.com>
Initialize platform driver data in the probe in order to be
able to fetch the data in adc_freeze and adc_restore callbacks.
Change-Id: Iacee302f2fae1d206838aec4aa40c22c046e353c
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Some qmi clients have low latency requirement. In high system
load, RX flow control bit set on RX DATA and its not consumed
by kernel qmi data thread which leads to timeout.
Adding high priority flag while allocating qmi work queue.
Change-Id: I64ba90777d3337849113ae4163f997bb781fbd40
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Add support for PHY interrupts and read pin control.
Change-Id: I38b20abcd1bb967bde396b539f5f5de5f5da1c9b
Signed-off-by: Sarosh Hasan <quic_sarohasa@quicinc.com>
The change adds a marker information for the display
restore from hibernation.
Change-Id: Iaf38c61f7ef43665981430bacf9776ef4b94cad8
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
In current implementation upon 3 wakeup interrupts,
uart driver is injecting 0xFD wakeup byte to BT. If
there are spurious wakeup interrupts, 0xFD is still
injected which is unexpected by BT host and BT assert
is seen.
To mitigate above scenario change handling of wakeup
interrupt mechanism as below:
1. Upon wakeup interrupt wake up UART driver out of suspend
2. Check if UART driver received the wakeup_byte
3. If wakeup byte is received send it to BT application
4. Else drop the rx bytes until wakeup byte 0xFD is received
5. If no wakeup byte received go back to suspend.
Change-Id: Ia0e2254aea748ebfab3ea3cec69708361cc20cef
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
CONFIG_CFG80211_CRDA_SUPPORT along with self managed regulatory
drivers/firmware blocks country set from user while waiting for
CRDA user modules to set country code/reg rules. This further leads
to SoftAp turn on delay as userspace keeps waiting for country code
CONFIG_CFG80211_CRDA_SUPPORT is enabled by default. Disable this
config for self managed regulatory drivers/firmware.
Change-Id: I7dbafa69b5b372b91bedc4f12861b5b989c0edea
Signed-off-by: Sandeep Singh <quic_sandsing@quicinc.com>
Add entries to support WPSS boot for qca6750 in cliffs using
RPROC.
Change-Id: Ibcd8e21c750f22653ee0accf892ca1d42fb23198
Signed-off-by: Prateek Patil <quic_pratpati@quicinc.com>
This patch adds the CDSP1, GPDSP0 and GPDSP1 subsystems to
subsystems list to get their sleep stats as part of
qcom_stats.
Change-Id: I2c37a3d58d77e9aa70e0591f54023169f854884c
Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
