Merge "phy: qualcomm: Add UFS PHY support for holi"
This commit is contained in:
qctecmdr
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9627cb010b
@ -58,7 +58,7 @@ config PHY_QCOM_QMP
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Enable this to support the QMP PHY transceiver that is used
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with controllers such as PCIe, UFS, and USB on Qualcomm chips.
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config PHY_QCOM_UFS
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menuconfig PHY_QCOM_UFS
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tristate "Qualcomm Technologies, Inc. UFS PHY driver"
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depends on OF && ARCH_QCOM
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select GENERIC_PHY
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@ -80,6 +80,14 @@ config PHY_QCOM_UFS_V3
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Support for 11nm UFS QMP phy present on QCOM chipsets.
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This is required to enable UFS on Sdmsteppe chipset.
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config PHY_QCOM_UFS_V3_SM4350
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tristate "Qualcomm Technologies, Inc. UFS Holi Phy Driver"
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help
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Qualcomm Technologies, Inc. UFS Holi Phy Driver.
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Enables support for UFS PHY on Qualcomm Technologies, Inc.
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Holi chipsets. This is required to enable UFS on Holi chipset.
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To compile this driver as a module, choose M here.
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config PHY_QCOM_UFS_V4
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tristate
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default PHY_QCOM_UFS
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@ -97,7 +105,6 @@ config PHY_QCOM_UFS_QRBTC_SDM845
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config PHY_QCOM_UFS_V4_SM6375
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tristate "Qualcomm Technologies, Inc. UFS Blair Phy Driver"
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depends on PHY_QCOM_UFS
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help
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Support for UFS phy present on QCOM Blair chipsets.
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@ -10,6 +10,7 @@ obj-$(CONFIG_PHY_QCOM_UFS_V4) += phy-qcom-ufs-qmp-v4-kalama.o phy-qcom-ufs-qmp-
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obj-$(CONFIG_PHY_QCOM_UFS_V3) += phy-qcom-ufs-qmp-v3-660.o
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obj-$(CONFIG_PHY_QCOM_UFS_QRBTC_SDM845) += phy-qcom-ufs-qrbtc-sdm845.o
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obj-$(CONFIG_PHY_QCOM_UFS_V4_SM6375) += phy-qcom-ufs-qmp-v4-blair.o
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obj-$(CONFIG_PHY_QCOM_UFS_V3_SM4350) += phy-qcom-ufs-qmp-v3.o
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obj-$(CONFIG_PHY_QCOM_QMP) += \
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phy-qcom-qmp.o \
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272
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c
Normal file
272
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c
Normal file
@ -0,0 +1,272 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "phy-qcom-ufs-qmp-v3.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_v3"
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static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy);
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static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common);
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static int ufs_qcom_phy_qmp_v3_phy_calibrate(struct phy *generic_phy)
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{
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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struct device *dev = ufs_qcom_phy->dev;
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bool is_rate_B;
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int err;
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err = reset_control_assert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to assert UFS PHY reset %d\n", err);
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goto out;
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}
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is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
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/*
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* Writing PHY calibration in this order:
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* 1. Write Rate-A calibration first (1-lane mode).
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* 2. Write 2nd lane configuration if needed.
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* 3. Write Rate-B calibration overrides
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*/
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
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ARRAY_SIZE(phy_cal_table_rate_A));
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if (ufs_qcom_phy->lanes_per_direction == 2)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane,
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ARRAY_SIZE(phy_cal_table_2nd_lane));
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if (is_rate_B)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
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ARRAY_SIZE(phy_cal_table_rate_B));
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/* flush buffered writes */
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mb();
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err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
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goto out;
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}
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ufs_qcom_phy_qmp_v3_start_serdes(ufs_qcom_phy);
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err = ufs_qcom_phy_qmp_v3_is_pcs_ready(ufs_qcom_phy);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v3_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_v3 *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err;
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err = ufs_qcom_phy_init_clks(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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/* Optional */
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ufs_qcom_phy_get_reset(phy_common);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v3_exit(struct phy *generic_phy)
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{
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return 0;
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}
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static
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int ufs_qcom_phy_qmp_v3_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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phy_common->submode = submode;
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return 0;
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}
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static
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void ufs_qcom_phy_qmp_v3_power_control(struct ufs_qcom_phy *phy,
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bool power_ctrl)
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{
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if (!power_ctrl) {
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/* apply analog power collapse */
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Make sure that PHY knows its analog rail is going to be
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* powered OFF.
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*/
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mb();
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} else {
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/* bring PHY out of analog power collapse */
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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}
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}
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static inline
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void ufs_qcom_phy_qmp_v3_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* v3 PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static
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void ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
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{
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u32 temp;
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temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
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if (ctrl) /* enable RX LineCfg */
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temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
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else /* disable RX LineCfg */
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temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
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writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
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/* make sure that RX LineCfg config applied before we return */
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mb();
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}
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static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err) {
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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goto out;
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}
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out:
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return err;
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}
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static void ufs_qcom_phy_qmp_v3_dbg_register_dump(struct ufs_qcom_phy *phy)
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{
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ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
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"PHY QSERDES COM Registers ");
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ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
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"PHY Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
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"PHY RX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
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"PHY TX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
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"PHY RX1 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
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"PHY TX1 Registers ");
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}
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static const struct phy_ops ufs_qcom_phy_qmp_v3_phy_ops = {
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.init = ufs_qcom_phy_qmp_v3_init,
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.exit = ufs_qcom_phy_qmp_v3_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.set_mode = ufs_qcom_phy_qmp_v3_set_mode,
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.calibrate = ufs_qcom_phy_qmp_v3_phy_calibrate,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_v3_ops = {
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.start_serdes = ufs_qcom_phy_qmp_v3_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v3_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_v3_set_tx_lane_enable,
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.ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg,
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.power_control = ufs_qcom_phy_qmp_v3_power_control,
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.dbg_register_dump = ufs_qcom_phy_qmp_v3_dbg_register_dump,
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};
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static int ufs_qcom_phy_qmp_v3_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_v3 *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_v3_phy_ops, &phy_v3_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strscpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_v3_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-v3"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_v3_driver = {
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.probe = ufs_qcom_phy_qmp_v3_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_v3_of_match,
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.name = "ufs_qcom_phy_qmp_v3",
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_v3_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3");
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MODULE_LICENSE("GPL");
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309
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h
Normal file
309
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h
Normal file
@ -0,0 +1,309 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef UFS_QCOM_PHY_QMP_V3_H_
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#define UFS_QCOM_PHY_QMP_V3_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_BASE 0x000
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#define COM_SIZE 0x18C
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#define PHY_BASE 0xC00
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#define PHY_SIZE 0x1DC
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#define TX_BASE(n) (0x400 + (0x400 * n))
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#define TX_SIZE 0x128
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#define RX_BASE(n) (0x600 + (0x400 * n))
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#define RX_SIZE 0x1FC
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#define COM_OFF(x) (COM_BASE + x)
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#define PHY_OFF(x) (PHY_BASE + x)
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#define TX_OFF(n, x) (TX_BASE(n) + x)
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#define RX_OFF(n, x) (RX_BASE(n) + x)
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/* UFS PHY QSERDES COM registers */
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#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00)
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#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04)
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#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08)
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#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
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#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10)
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#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14)
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#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18)
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#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C)
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#define QSERDES_COM_SSC_PER2 COM_OFF(0x20)
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#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24)
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#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28)
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#define QSERDES_COM_POST_DIV COM_OFF(0x2C)
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#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
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#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38)
|
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
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#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40)
|
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#define QSERDES_COM_PLL_EN COM_OFF(0x44)
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#define QSERDES_COM_PLL_IVCO COM_OFF(0x48)
|
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|
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/* UFS PHY registers */
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#define UFS_PHY_PHY_START PHY_OFF(0x00)
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#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
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#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08)
|
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#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C)
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#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x2C)
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#define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x30)
|
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#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x34)
|
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#define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x38)
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#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x130)
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#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134)
|
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#define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x138)
|
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#define UFS_PHY_RX_SIGDET_CTRL1 PHY_OFF(0x13C)
|
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#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x140)
|
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#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x14C)
|
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#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x160)
|
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#define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1BC)
|
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#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1C4)
|
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#define QSERDES_COM_CMN_IETRIM COM_OFF(0x4C)
|
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#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x50)
|
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#define QSERDES_COM_EP_CLOCK_DETECT_CTR COM_OFF(0x54)
|
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#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x58)
|
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#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x5C)
|
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#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x60)
|
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#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x64)
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x68)
|
||||
#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x6C)
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x70)
|
||||
#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x74)
|
||||
#define QSERDES_COM_PLL_CNTRL COM_OFF(0x78)
|
||||
#define SERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0x7C)
|
||||
#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x80)
|
||||
#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0x84)
|
||||
#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x88)
|
||||
#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x8C)
|
||||
#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x90)
|
||||
#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0x94)
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x98)
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x9C)
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0xA0)
|
||||
#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xA4)
|
||||
#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xA8)
|
||||
#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0xAC)
|
||||
#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xB0)
|
||||
#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xB4)
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xB8)
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xBC)
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xC0)
|
||||
#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xC4)
|
||||
#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xC8)
|
||||
#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xCC)
|
||||
#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0xD0)
|
||||
#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0xD4)
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0xD8)
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0xDC)
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0xE0)
|
||||
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0xE4)
|
||||
#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xE8)
|
||||
#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0xEC)
|
||||
#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0xF0)
|
||||
#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0xF4)
|
||||
#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0xF8)
|
||||
#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0xFC)
|
||||
#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x100)
|
||||
#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x104)
|
||||
#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x108)
|
||||
#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0x10C)
|
||||
#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0x110)
|
||||
#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x114)
|
||||
#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x118)
|
||||
#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x11C)
|
||||
#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x120)
|
||||
#define QSERDES_COM_CMN_STATUS COM_OFF(0x124)
|
||||
#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x128)
|
||||
#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x12C)
|
||||
#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x130)
|
||||
#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x134)
|
||||
#define QSERDES_COM_CLK_SELECT COM_OFF(0x138)
|
||||
#define QSERDES_COM_HSCLK_SEL COM_OFF(0x13C)
|
||||
#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x140)
|
||||
#define QSERDES_COM_PLL_ANALOG COM_OFF(0x144)
|
||||
#define QSERDES_COM_CORECLK_DIV_MODE0 COM_OFF(0x148)
|
||||
#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x14C)
|
||||
#define QSERDES_COM_SW_RESET COM_OFF(0x150)
|
||||
#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x154)
|
||||
#define QSERDES_COM_C_READY_STATUS COM_OFF(0x158)
|
||||
#define QSERDES_COM_CMN_CONFIG COM_OFF(0x15C)
|
||||
#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x160)
|
||||
#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x164)
|
||||
#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x168)
|
||||
#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x16C)
|
||||
#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x170)
|
||||
#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x174)
|
||||
#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x178)
|
||||
#define QSERDES_COM_CMN_MISC1 COM_OFF(0x17C)
|
||||
#define QSERDES_COM_CMN_MISC2 COM_OFF(0x180)
|
||||
#define QSERDES_COM_CMN_MODE COM_OFF(0x184)
|
||||
#define QSERDES_COM_CMN_VREG_SEL COM_OFF(0x188)
|
||||
|
||||
/* UFS PHY TX registers */
|
||||
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x44)
|
||||
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x48)
|
||||
#define QSERDES_TX0_TRANSCEIVER_BIAS_EN TX_OFF(0, 0x5C)
|
||||
#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x8C)
|
||||
#define QSERDES_TX0_LANE_MODE_2 TX_OFF(0, 0x90)
|
||||
#define QSERDES_TX0_LANE_MODE_3 TX_OFF(0, 0x94)
|
||||
|
||||
#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x44)
|
||||
#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x48)
|
||||
#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x8C)
|
||||
|
||||
|
||||
/* UFS PHY RX registers */
|
||||
#define QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF RX_OFF(0, 0x24)
|
||||
#define QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0, 0x28)
|
||||
#define QSERDES_RX0_UCDR_SVS_SO_GAIN RX_OFF(0, 0x2C)
|
||||
#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
|
||||
#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
|
||||
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
|
||||
#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
|
||||
#define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x7C)
|
||||
#define QSERDES_RX0_RX_EQ_GAIN2_LSB RX_OFF(0, 0xC8)
|
||||
#define QSERDES_RX0_RX_EQ_GAIN2_MSB RX_OFF(0, 0xCC)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(0, 0xD0)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD4)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xD8)
|
||||
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xDC)
|
||||
#define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x104)
|
||||
#define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x108)
|
||||
#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x10C)
|
||||
#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x11C)
|
||||
#define QSERDES_RX0_RX_MODE_00 RX_OFF(0, 0x164)
|
||||
#define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08)
|
||||
|
||||
#define QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF RX_OFF(1, 0x24)
|
||||
#define QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(1, 0x28)
|
||||
#define QSERDES_RX1_UCDR_SVS_SO_GAIN RX_OFF(1, 0x2C)
|
||||
#define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN RX_OFF(1, 0x30)
|
||||
#define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(1, 0x34)
|
||||
#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW RX_OFF(1, 0x3C)
|
||||
#define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0x44)
|
||||
#define QSERDES_RX1_RX_TERM_BW RX_OFF(1, 0x7C)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(1, 0xD4)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(1, 0xD8)
|
||||
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0xDC)
|
||||
#define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x104)
|
||||
#define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x108)
|
||||
#define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL RX_OFF(1, 0x10C)
|
||||
#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x11C)
|
||||
#define QSERDES_RX1_RX_MODE_00 RX_OFF(1, 0x164)
|
||||
#define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x8)
|
||||
|
||||
#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
|
||||
|
||||
/*
|
||||
* This structure represents the v3 specific phy.
|
||||
* common_cfg MUST remain the first field in this structure
|
||||
* in case extra fields are added. This way, when calling
|
||||
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||
* common phy structure (struct ufs_qcom_phy) out of it
|
||||
* regardless of the relevant specific phy.
|
||||
*/
|
||||
struct ufs_qcom_phy_qmp_v3 {
|
||||
struct ufs_qcom_phy common_cfg;
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xDA),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xC1),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00, 0x59),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),/* 13 us */
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_INTERFACE_MODE, 0x40),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x5B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x81),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x04),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x07),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00, 0x59),
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C),
|
||||
};
|
||||
|
||||
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user