Commit Graph

3179 Commits

Author SHA1 Message Date
Raviteja Laggyshetty
67dca5fb44 icc: dt-bindings: add endpoint IDs for interconnects for VOLCANO
Add master and slave ID constants for all Qualcomm Technologies, Inc.
Volcano interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I212e4a1409d06cb852f357b050e6a12cac1162d5
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-12-18 19:05:50 -08:00
qctecmdr
7cf84956f6 Merge "icc: dt-bindings: Add end point IDs for ddr_rt nodes for NIOBE" 2023-12-17 23:24:58 -08:00
Kalpak Kawadkar
c99fa8afe7 bindings: clock: gpucc: Add support for LIMITER reset
Add support for the consumer to be able to set/reset the
GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR register as required on
BLAIR and HOLI platforms.

Change-Id: I0d041066e36c0152fdcc8e306367aebdc5fd6283
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-12-06 20:51:00 -08:00
qctecmdr
065e2a624d Merge "bindings: clock: qcom: Add support for clock IDs for volcano" 2023-12-06 10:51:05 -08:00
qctecmdr
02d89ece11 Merge "bindings: clock: tcsrcc: Update PCIE and USB clkref IDs" 2023-12-01 07:00:23 -08:00
Kalpak Kawadkar
9bae41cbd7 bindings: clock: tcsrcc: Update PCIE and USB clkref IDs
Update PCIE and USB clkref IDs as per latest HW recommendation
on NIOBE platform.

Change-Id: Ib564a0ef3f49a04c6ef8cf564c661ec512fb4afe
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-12-01 11:41:30 +05:30
Sidharth Suresh
f62db22610 dt-binding: qcom: Add client IDs for SAIL
Add client IDs for SAIL-APSS communication.

Change-Id: I1976d8606b3f96b8681b5d255d70f2845dfe5711
Signed-off-by: Sidharth Suresh <quic_sidhsure@quicinc.com>
2023-11-30 16:47:36 -08:00
Raviteja Laggyshetty
77654cdbe9 icc: dt-bindings: Add end point IDs for ddr_rt nodes for NIOBE
DDR_RT node support is required for RT clients to vote for minimum
DDR frequency.

Change-Id: I47371cf09597a81b6f2c89669f45417314801074
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-11-29 18:02:41 +05:30
qctecmdr
398a6df173 Merge "interconnect: qcom: Add interconnect providers for NIOBE" 2023-11-25 03:11:21 -08:00
Raviteja Laggyshetty
7cd41d93db icc: dt-bindings: update lpass endpoint IDs for interconnects for NIOBE
Add master and slave ID constants for lpass_ag_noc interconnect
provider, which consumers can use to set bandwidth constraints and
find paths in the NoC (Network-On-Chip) topology.

Change-Id: I24c46501573afb5ccf8eeb5d42d9c684cda95784
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-11-21 14:28:28 +05:30
Raviteja Laggyshetty
3121ff2ea4 icc: dt-bindings: add endpoint IDs for interconnects for PITTI
Add master and slave ID constants for all Qualcomm Technologies, Inc.
Pitti interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I7bc06ae5b1f318041c750e3ce56e8cdc3f53f2bf
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-11-20 20:08:58 -08:00
Ajit Pandey
7555920df5 bindings: clock: qcom: Add support for clock IDs for volcano
Add the clock handles for CAMCC/DISPCC/GCC/GPUCC/VIDEOCC, so
that the clients can request on the clock ids.

Change-Id: Id9f72c77d34e4aa48394c087282b748573cdc131
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
2023-11-20 15:31:34 +05:30
qctecmdr
bdd976626c Merge "interconnect: qcom: add secondary display nodes to topology for NIOBE" 2023-11-10 18:40:13 -08:00
qctecmdr
a48bfb0537 Merge "dt-bindings: mailbox: Add SOCCP and BROADCAST clients" 2023-11-09 23:59:32 -08:00
Kishore Kumar Ravi
85b0d452fd dt-bindings: mailbox: Add SOCCP and BROADCAST clients
Add clients for SOCCP and BROADCAST in Niobe SoC.

Change-Id: I61ea5a1e27696f397d472ee6d44c12c2208ee9c9
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
2023-11-09 16:04:23 +05:30
Raviteja Laggyshetty
9e860fa30f icc: dt-bindings: add endpoint IDs for second display for NIOBE
Added master and slave interconnect node IDs related to second
display to topology. These IDs are used by display consumers to set
bandwidth constraints and find path in NOC topology.

Change-Id: Ic9198df700722e686ee49864a34a2442903b9a4e
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-11-08 17:52:08 +05:30
qctecmdr
7dc4ec365f Merge "dt-bindings: thermal: Add modem QFE_RET sensors" 2023-11-08 01:21:06 -08:00
qctecmdr
6b42209175 Merge "clk: qcom: gpucc-cliffs: Add support for freq limiter reset" 2023-11-08 01:21:05 -08:00
Nitesh Kumar
602ca8c527 dt-bindings: thermal: Add modem QFE_RET sensors
Add modem qfe_ret_pa, qfe_wtr_pa sensor in thermal qti header.

Change-Id: I95a48c31d61c491878636515211b9516f6f7e70e
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>
2023-11-08 00:58:00 +05:30
qctecmdr
753cfd5a64 Merge "bindings: clock: gpucc: Add support for gx clock IDs" 2023-11-02 06:39:02 -07:00
qctecmdr
121a68cd74 Merge "icc: dt-bindings: add endpoint IDs for interconnects for NIOBE" 2023-11-01 08:45:28 -07:00
Raviteja Laggyshetty
9767846c81 icc: dt-bindings: add endpoint IDs for interconnects for NIOBE
Add master and slave ID constants for all Qualcomm Technologies, Inc.
Niobe interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I36005b260191826f73d3cb7f4a310f369b3f4292
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-11-01 11:08:48 +05:30
Kalpak Kawadkar
ab003d0b06 bindings: clock: gpucc: Add support for gx clock IDs
Add support for gx clock IDs on NIOBE platform.

Change-Id: I70d4353f322e0402d2e363947a1e49d0b8d48ef0
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-10-30 15:39:13 +05:30
Raviteja Laggyshetty
94c668190a icc: dt-bindings: Add apss_noc and cnoc_data master IDs for CLIFFS
Added qnm_apss_noc and qnm_cnoc_data master IDs to topolgy for
programming qos.

Change-Id: I9a5183f063d3d3691ee0592949a83c4560b63b1b
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-10-30 08:43:49 +05:30
qctecmdr
6cee6ab461 Merge "bindings: clock: qcom: Update videocc reset IDs on NIOBE" 2023-10-13 05:20:51 -07:00
Jagadeesh Kona
3972e5db48 dt-bindings: clock: gpucc-cliffs: Add support for freq limiter reset
Add support for the consumer to be able to set/reset the
GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR register as an when required on
cliffs platform.

Change-Id: Ic840fd9ae97ec89ded435bb75081272a5035ebec
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
2023-10-11 12:12:53 +05:30
Kalpak Kawadkar
eb5304805d bindings: clock: qcom: Update videocc reset IDs on NIOBE
Update video clock controller reset IDs on NIOBE platform.

Change-Id: Idff065fea7570e22c5b0a0fc6d889f837ff2b13b
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-10-10 15:51:23 +05:30
Imran Shaik
8d72e66f96 bindings: clock: gcc-pitti: Update GCC clocks and resets
Add support for GCC_DISP_GPLL0_CLK_SRC clock and venus clock resets
on PITTI platform.

Change-Id: Ie439131c7e64a952b7f560300777360e8a402634
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
2023-10-05 09:51:10 +05:30
qctecmdr
1f4f6f1f92 Merge "dt-bindings: iio: Add ADC5 GEN3 ICHG_FB channel for PM7550BA" 2023-10-02 14:59:25 -07:00
qctecmdr
d7bd249603 Merge "dt-bindings: iio: Add ADC support for PMXR2230" 2023-10-02 03:35:58 -07:00
Anjelique Melendez
bc2ffff6ec dt-bindings: iio: Add ADC5 GEN3 ICHG_FB channel for PM7550BA
Add ADC5 GEN3 ICHG_FB channel used by PM7550BA.

Change-Id: Id4decfbf031b1ed9eb26a9f793fe8a0cb7f1075a
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
2023-09-29 03:30:14 -07:00
Anjelique Melendez
b5884279b0 dt-bindings: iio: Add ADC5 GEN3 channels for PM7550BA and PMX75
Add the ADC5 GEN3 channels used by PM7550BA and PMX75.

Change-Id: I64836a6ad9ab5b440f87f58f2f272e50a7e47e7a
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
2023-09-28 23:47:25 -07:00
Jishnu Prakash
8ff4028e4f dt-bindings: iio: Add ADC support for PMXR2230
Add virtual channel definitions for PMXR2230 for
use by its ADC clients.

Change-Id: I3f184b45380d61ff4057449007baf0f6e94e5e0f
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
2023-09-26 11:14:35 +05:30
Kalpak Kawadkar
b2e6829e21 bindings: clock: gcc-holi: Add support for venus clock resets
Add support for gcc venus clock resets on HOLI platform.

Change-Id: I033843f5a0195aede3eeb8cd45e866d5ca25da9c
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-09-26 10:21:57 +05:30
Kalpak Kawadkar
ca18f5f9e0 dt-bindings: clock: Add support for GCC clocks on NIOBE
Add support of GCC_AGGRE_USB3_SEC_AXI_CLK, GCC_PCIE_1_PHY_AUX_CLK,
GCC_PCIE_1_PHY_AUX_CLK_SRC and GCC_USB30_PRIM_ATB_CLK clocks
on NIOBE platform.

Change-Id: I3587a847faa27f047abd5fe233cbc5e214ad6ce4
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-09-13 17:25:55 +05:30
qctecmdr
6b86b2e69c Merge "arm64: defconfig: Enable common clock and gdsc regulator drivers for PITTI" 2023-08-31 20:44:37 -07:00
qctecmdr
aea891477e Merge "interconnect: qcom: Update QUP endpoint IDs for CLIFFS" 2023-08-29 08:37:01 -07:00
qctecmdr
b0ccf9a79b Merge "dt-bindings: qcom: ipcc: Add SoCCP definitions" 2023-08-25 05:50:22 -07:00
qctecmdr
b6c8e3de97 Merge "interconnect: qcom: pineapple: Add qnm_apss_noc node" 2023-08-24 01:55:43 -07:00
Kishore Kumar Ravi
fb58833236 dt-bindings: qcom: ipcc: Add SoCCP definitions
Update the ipcc dt-bindings header to include definitions for the soccp
client and increase the max IPCC client value.

Change-Id: I452f966e37f623f7e35fee4496a0b374f974f4cb
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
2023-08-24 12:59:01 +05:30
Imran Shaik
cfa1d19ece bindings: clock: qcom: Add support for clock IDs for PITTI
Add the clock handles for GCC/GPUCC/DISPCC, so that the clients
can request on the clock ids on PITTI platform.

Change-Id: Ie19a1abd348e90599963d4247d15ae77895d9c09
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
2023-08-23 21:03:21 +05:30
qctecmdr
97ad78d3a0 Merge "usb: dt-bindings: Add Snapshot of USB QMP PHY used for 8NM Soc" 2023-08-23 02:15:06 -07:00
qctecmdr
d21c67607c Merge "module.list.msm.blair: Add qnoc-holi driver to module list for HOLI" 2023-08-22 04:31:54 -07:00
Raviteja Laggyshetty
7373eb56e7 icc: dt-bindings: Update endpoint IDs for QUP nodes for CLIFFS
Updated QUP endpoints ID macros in NOC topology to match with
QUP firmware.

Change-Id: Ie3005669246ec084339277d691681b5986ec5573
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-08-21 15:16:36 +05:30
Udipto Goswami
b60b47220c usb: dt-bindings: Add Snapshot of USB QMP PHY used for 8NM Soc
Add Snapshot of  the dt bindings for the qmp phy used on targets
based on 8LPU node.
This is based on msm-5.4 commit 51ed8d4bd63b ("dt-bindings: Add
macros for defining USB QMP PHY registers").

Change-Id: Iee392038e36452822ff6539ca6bc467d95ce1827
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
2023-08-18 01:55:49 -07:00
Mike Tipton
f206156a49 dt-bindings: interconnect: Add MASTER_APSS_NOC for Pineapple
Add binding for the MASTER_APSS_NOC port.

Change-Id: Ie87dc75af7c3f7614360a6d68cd5e09d107a9877
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
2023-08-15 18:28:27 -07:00
qctecmdr
9ce4ea145c Merge "bindings: clock: qcom: Add support of TSCSRCC clock IDs for NIOBE" 2023-08-14 10:45:02 -07:00
Kalpak Kawadkar
11220cb3a1 bindings: clock: qcom: Add support of TSCSRCC clock IDs for NIOBE
Add the clock handles for TCSRCC, so that the clients can request
on these clocks for NIOBE platform.

Change-Id: I46d7fa2a4069319b077ae3a11c1e7a483aecd7d7
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-08-10 16:01:04 +05:30
Kalpak Kawadkar
e4e9db7939 dt-bindings: clock: Update clock id of GCC_DISP_GPLL0_CLK_SRC on HOLI
Update clock id of GCC_DISP_GPLL0_CLK_SRC to correct name on HOLI.

Change-Id: Id792eace49beab184afbb31e6c17fb67f04e94f8
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
2023-08-06 14:14:09 +05:30
Raviteja Laggyshetty
653e0f9057 icc: dt-bindings: add endpoint IDs for interconnects for HOLI
Add master and slave ID constants for all Qualcomm Technologies, Inc.
Holi interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I3c561381a3a13566b7a0503dc4e55b0c490be7c4
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
2023-08-03 09:25:45 -07:00