Merge "interconnect: qcom: Add interconnect providers for NIOBE"
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qctecmdr
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398a6df173
@ -386,16 +386,17 @@ static struct qcom_icc_node qnm_gemnoc_cnoc = {
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 18,
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.num_links = 19,
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.links = { SLAVE_AOSS, SLAVE_APPSS,
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SLAVE_DISPLAY1_CFG, SLAVE_DISPLAY_CFG,
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SLAVE_GFX3D_CFG, SLAVE_IPA_CFG,
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SLAVE_IPC_ROUTER_CFG, SLAVE_PCIE_0_CFG,
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SLAVE_PCIE_1_CFG, SLAVE_PCIE_2_CFG,
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SLAVE_SOCCP, SLAVE_TME_CFG,
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SLAVE_CNOC_CFG, SLAVE_DDRSS_CFG,
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SLAVE_BOOT_IMEM, SLAVE_BOOT_IMEM_2,
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SLAVE_IMEM, SLAVE_SERVICE_CNOC },
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SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS,
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SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG,
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SLAVE_PCIE_2_CFG, SLAVE_SOCCP,
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SLAVE_TME_CFG, SLAVE_CNOC_CFG,
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SLAVE_DDRSS_CFG, SLAVE_BOOT_IMEM,
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SLAVE_BOOT_IMEM_2, SLAVE_IMEM,
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SLAVE_SERVICE_CNOC },
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};
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static struct qcom_icc_node qnm_gemnoc_pcie = {
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@ -486,6 +487,29 @@ static struct qcom_icc_node qnm_gpu = {
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC },
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};
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static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 1,
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.offsets = { 0xb5000 },
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.config = &(struct qos_config) {
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.prio = 0,
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.urg_fwd = 1,
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.prio_fwd_disable = 0,
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},
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};
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static struct qcom_icc_node qnm_lpass_gemnoc = {
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.name = "qnm_lpass_gemnoc",
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.id = MASTER_LPASS_GEM_NOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.qosbox = &qnm_lpass_gemnoc_qos,
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.num_links = 3,
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.links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC,
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SLAVE_MEM_NOC_PCIE_SNOC },
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};
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static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
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.regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH],
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.num_ports = 2,
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@ -620,6 +644,29 @@ static struct qcom_icc_node xm_gic = {
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.links = { SLAVE_LLCC },
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};
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static struct qcom_icc_node qhm_config_noc = {
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.name = "qhm_config_noc",
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.id = MASTER_CNOC_LPASS_AG_NOC,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 6,
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.links = { SLAVE_LPASS_CORE_CFG, SLAVE_LPASS_LPI_CFG,
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SLAVE_LPASS_MPU_CFG, SLAVE_LPASS_TOP_CFG,
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SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC },
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};
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static struct qcom_icc_node qxm_lpass_dsp = {
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.name = "qxm_lpass_dsp",
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.id = MASTER_LPASS_PROC,
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.channels = 1,
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.buswidth = 8,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 4,
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.links = { SLAVE_LPASS_TOP_CFG, SLAVE_LPASS_GEM_NOC,
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SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC },
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};
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static struct qcom_icc_node llcc_mc = {
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.name = "llcc_mc",
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.id = MASTER_LLCC,
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@ -1591,6 +1638,16 @@ static struct qcom_icc_node qhs_ipc_router = {
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.num_links = 0,
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};
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static struct qcom_icc_node qhs_lpass_cfg = {
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.name = "qhs_lpass_cfg",
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.id = SLAVE_LPASS,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { MASTER_CNOC_LPASS_AG_NOC },
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};
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static struct qcom_icc_node qhs_pcie3_0_cfg = {
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.name = "qhs_pcie3_0_cfg",
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.id = SLAVE_PCIE_0_CFG,
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@ -1748,6 +1805,70 @@ static struct qcom_icc_node qns_pcie = {
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.links = { MASTER_GEM_NOC_PCIE_SNOC },
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};
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static struct qcom_icc_node qhs_lpass_core = {
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.name = "qhs_lpass_core",
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.id = SLAVE_LPASS_CORE_CFG,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node qhs_lpass_lpi = {
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.name = "qhs_lpass_lpi",
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.id = SLAVE_LPASS_LPI_CFG,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node qhs_lpass_mpu = {
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.name = "qhs_lpass_mpu",
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.id = SLAVE_LPASS_MPU_CFG,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node qhs_lpass_top = {
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.name = "qhs_lpass_top",
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.id = SLAVE_LPASS_TOP_CFG,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
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.name = "qns_lpass_ag_noc_gemnoc",
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.id = SLAVE_LPASS_GEM_NOC,
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.channels = 1,
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.buswidth = 16,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 1,
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.links = { MASTER_LPASS_GEM_NOC },
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};
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static struct qcom_icc_node srvc_niu_aml_noc = {
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.name = "srvc_niu_aml_noc",
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.id = SLAVE_SERVICES_LPASS_AML_NOC,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node srvc_niu_lpass_agnoc = {
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.name = "srvc_niu_lpass_agnoc",
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.id = SLAVE_SERVICE_LPASS_AG_NOC,
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.channels = 1,
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.buswidth = 4,
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.noc_ops = &qcom_qnoc4_ops,
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.num_links = 0,
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};
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static struct qcom_icc_node ebi = {
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.name = "ebi",
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.id = SLAVE_EBI1,
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@ -2031,7 +2152,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
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.voter_idx = VOTER_IDX_HLOS,
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.enable_mask = 0x1,
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.keepalive = true,
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.num_nodes = 47,
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.num_nodes = 48,
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.nodes = { &qsm_cfg, &qhs_ahb2phy0,
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&qhs_ahb2phy1, &qhs_ahb2phy2,
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&qhs_camera_cfg, &qhs_clk_ctl,
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@ -2048,14 +2169,14 @@ static struct qcom_icc_bcm bcm_cn0 = {
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&qhs_aoss, &qhs_apss,
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&qhs_display1_cfg, &qhs_display_cfg,
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&qhs_gpuss_cfg, &qhs_ipa,
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&qhs_ipc_router, &qhs_pcie3_0_cfg,
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&qhs_pcie4_1_cfg, &qhs_pcie4_0_cfg,
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&qhs_soccp, &qhs_tme_cfg,
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&qss_cfg, &qss_ddrss_cfg,
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&qxs_boot_imem, &qxs_boot_imem2,
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&qxs_imem, &srvc_cnoc_main,
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&xs_pcie3_0, &xs_pcie4_1,
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&xs_pcie4_0 },
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&qhs_ipc_router, &qhs_lpass_cfg,
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&qhs_pcie3_0_cfg, &qhs_pcie4_1_cfg,
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&qhs_pcie4_0_cfg, &qhs_soccp,
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&qhs_tme_cfg, &qss_cfg,
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&qss_ddrss_cfg, &qxs_boot_imem,
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&qxs_boot_imem2, &qxs_imem,
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&srvc_cnoc_main, &xs_pcie3_0,
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&xs_pcie4_1, &xs_pcie4_0 },
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};
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static struct qcom_icc_bcm bcm_cn1 = {
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@ -2543,6 +2664,7 @@ static struct qcom_icc_node *cnoc_main_nodes[] = {
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[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
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[SLAVE_IPA_CFG] = &qhs_ipa,
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[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
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[SLAVE_LPASS] = &qhs_lpass_cfg,
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[SLAVE_PCIE_0_CFG] = &qhs_pcie3_0_cfg,
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[SLAVE_PCIE_1_CFG] = &qhs_pcie4_1_cfg,
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[SLAVE_PCIE_2_CFG] = &qhs_pcie4_0_cfg,
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@ -2593,6 +2715,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = {
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[MASTER_SYS_TCU] = &alm_sys_tcu,
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[MASTER_APPSS_PROC] = &chm_apps,
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[MASTER_GFX3D] = &qnm_gpu,
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[MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
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[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
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[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
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[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
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@ -2640,6 +2763,15 @@ static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
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};
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static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
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[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
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[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
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[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
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[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
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[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
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[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
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[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
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[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
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[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
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};
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static char *lpass_ag_noc_voters[] = {
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@ -10,51 +10,54 @@
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_LLCC 3
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#define MASTER_QDSS_BAM 4
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#define MASTER_QUP_1 5
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#define MASTER_QUP_2 6
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#define MASTER_QUP_3 7
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#define MASTER_A1NOC_SNOC 8
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#define MASTER_A2NOC_SNOC 9
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#define MASTER_CAMNOC_HF 10
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#define MASTER_CAMNOC_ICP 11
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#define MASTER_CAMNOC_SF 12
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#define MASTER_GEM_NOC_CNOC 13
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#define MASTER_GEM_NOC_PCIE_SNOC 14
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#define MASTER_GFX3D 15
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#define MASTER_MDP0 16
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#define MASTER_MDP1 17
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#define MASTER_MNOC_HF_MEM_NOC 18
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#define MASTER_MNOC_SF_MEM_NOC 19
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#define MASTER_CDSP_PROC 20
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#define MASTER_COMPUTE_NOC 21
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#define MASTER_ANOC_PCIE_GEM_NOC 22
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#define MASTER_SNOC_SF_MEM_NOC 23
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#define MASTER_VIDEO 24
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#define MASTER_VIDEO_CV_PROC 25
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#define MASTER_VIDEO_PROC 26
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#define MASTER_VIDEO_V_PROC 27
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#define MASTER_CNOC_CFG 28
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#define MASTER_CNOC_MNOC_HF_CFG 29
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#define MASTER_PCIE_ANOC_CFG 30
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#define MASTER_CNOC_MNOC_SF_CFG 31
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#define MASTER_QUP_CORE_1 32
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#define MASTER_QUP_CORE_2 33
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#define MASTER_QUP_CORE_3 34
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#define MASTER_CRYPTO 35
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#define MASTER_IPA 36
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#define MASTER_SOCCP_AGGR_NOC 37
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#define MASTER_SP 38
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#define MASTER_GIC 39
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#define MASTER_PCIE_0 40
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#define MASTER_PCIE_2 41
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#define MASTER_PCIE_1 42
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#define MASTER_QDSS_ETR 43
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#define MASTER_QDSS_ETR_1 44
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#define MASTER_SDCC_2 45
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#define MASTER_UFS_MEM 46
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#define MASTER_USB3_0 47
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#define MASTER_USB3_1 48
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#define MASTER_CNOC_LPASS_AG_NOC 4
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#define MASTER_QDSS_BAM 5
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#define MASTER_QUP_1 6
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#define MASTER_QUP_2 7
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#define MASTER_QUP_3 8
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#define MASTER_A1NOC_SNOC 9
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#define MASTER_A2NOC_SNOC 10
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#define MASTER_CAMNOC_HF 11
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#define MASTER_CAMNOC_ICP 12
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#define MASTER_CAMNOC_SF 13
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#define MASTER_GEM_NOC_CNOC 14
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#define MASTER_GEM_NOC_PCIE_SNOC 15
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#define MASTER_GFX3D 16
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#define MASTER_LPASS_GEM_NOC 17
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#define MASTER_MDP0 18
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#define MASTER_MDP1 19
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#define MASTER_MNOC_HF_MEM_NOC 20
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#define MASTER_MNOC_SF_MEM_NOC 21
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#define MASTER_CDSP_PROC 22
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#define MASTER_COMPUTE_NOC 23
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#define MASTER_ANOC_PCIE_GEM_NOC 24
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#define MASTER_SNOC_SF_MEM_NOC 25
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#define MASTER_VIDEO 26
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#define MASTER_VIDEO_CV_PROC 27
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#define MASTER_VIDEO_PROC 28
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#define MASTER_VIDEO_V_PROC 29
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#define MASTER_CNOC_CFG 30
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#define MASTER_CNOC_MNOC_HF_CFG 31
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#define MASTER_PCIE_ANOC_CFG 32
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#define MASTER_CNOC_MNOC_SF_CFG 33
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#define MASTER_QUP_CORE_1 34
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#define MASTER_QUP_CORE_2 35
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#define MASTER_QUP_CORE_3 36
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#define MASTER_CRYPTO 37
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#define MASTER_IPA 38
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#define MASTER_LPASS_PROC 39
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#define MASTER_SOCCP_AGGR_NOC 40
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#define MASTER_SP 41
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#define MASTER_GIC 42
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#define MASTER_PCIE_0 43
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#define MASTER_PCIE_2 44
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#define MASTER_PCIE_1 45
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#define MASTER_QDSS_ETR 46
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#define MASTER_QDSS_ETR_1 47
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#define MASTER_SDCC_2 48
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#define MASTER_UFS_MEM 49
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#define MASTER_USB3_0 50
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#define MASTER_USB3_1 51
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#define SLAVE_EBI1 512
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#define SLAVE_AHB2PHY_SOUTH 513
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#define SLAVE_AHB2PHY_CENTER 514
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@ -70,55 +73,63 @@
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#define SLAVE_IMEM_CFG 524
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#define SLAVE_IPA_CFG 525
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#define SLAVE_IPC_ROUTER_CFG 526
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#define SLAVE_PCIE_0_CFG 527
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#define SLAVE_PCIE_2_CFG 528
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#define SLAVE_PCIE_1_CFG 529
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#define SLAVE_PRNG 530
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#define SLAVE_QDSS_CFG 531
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#define SLAVE_QUP_1 532
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#define SLAVE_QUP_2 533
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#define SLAVE_QUP_3 534
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#define SLAVE_SDCC_2 535
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#define SLAVE_SOCCP 536
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#define SLAVE_SPSS_CFG 537
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#define SLAVE_TCSR 538
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#define SLAVE_TLMM 539
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#define SLAVE_TME_CFG 540
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#define SLAVE_UFS_MEM_CFG 541
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#define SLAVE_USB3_0 542
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#define SLAVE_USB3_1 543
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#define SLAVE_VENUS_CFG 544
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#define SLAVE_VSENSE_CTRL_CFG 545
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#define SLAVE_A1NOC_SNOC 546
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#define SLAVE_A2NOC_SNOC 547
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#define SLAVE_GEM_NOC_CNOC 548
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#define SLAVE_SNOC_GEM_NOC_SF 549
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#define SLAVE_LLCC 550
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#define SLAVE_MNOC_HF_MEM_NOC 551
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#define SLAVE_MNOC_SF_MEM_NOC 552
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#define SLAVE_CDSP_MEM_NOC 553
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#define SLAVE_MEM_NOC_PCIE_SNOC 554
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#define SLAVE_ANOC_PCIE_GEM_NOC 555
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#define SLAVE_CNOC_CFG 556
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#define SLAVE_DDRSS_CFG 557
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#define SLAVE_CNOC_MNOC_HF_CFG 558
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#define SLAVE_CNOC_MNOC_SF_CFG 559
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#define SLAVE_PCIE_ANOC_CFG 560
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||||
#define SLAVE_QUP_CORE_1 561
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||||
#define SLAVE_QUP_CORE_2 562
|
||||
#define SLAVE_QUP_CORE_3 563
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||||
#define SLAVE_BOOT_IMEM 564
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||||
#define SLAVE_BOOT_IMEM_2 565
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||||
#define SLAVE_IMEM 566
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||||
#define SLAVE_SERVICE_CNOC 567
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||||
#define SLAVE_SERVICE_MNOC_HF 568
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#define SLAVE_SERVICE_MNOC_SF 569
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||||
#define SLAVE_SERVICE_PCIE_ANOC 570
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#define SLAVE_PCIE_0 571
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#define SLAVE_PCIE_2 572
|
||||
#define SLAVE_PCIE_1 573
|
||||
#define SLAVE_QDSS_STM 574
|
||||
#define SLAVE_TCU 575
|
||||
#define SLAVE_LPASS 527
|
||||
#define SLAVE_LPASS_CORE_CFG 528
|
||||
#define SLAVE_LPASS_LPI_CFG 529
|
||||
#define SLAVE_LPASS_MPU_CFG 530
|
||||
#define SLAVE_LPASS_TOP_CFG 531
|
||||
#define SLAVE_PCIE_0_CFG 532
|
||||
#define SLAVE_PCIE_2_CFG 533
|
||||
#define SLAVE_PCIE_1_CFG 534
|
||||
#define SLAVE_PRNG 535
|
||||
#define SLAVE_QDSS_CFG 536
|
||||
#define SLAVE_QUP_1 537
|
||||
#define SLAVE_QUP_2 538
|
||||
#define SLAVE_QUP_3 539
|
||||
#define SLAVE_SDCC_2 540
|
||||
#define SLAVE_SOCCP 541
|
||||
#define SLAVE_SPSS_CFG 542
|
||||
#define SLAVE_TCSR 543
|
||||
#define SLAVE_TLMM 544
|
||||
#define SLAVE_TME_CFG 545
|
||||
#define SLAVE_UFS_MEM_CFG 546
|
||||
#define SLAVE_USB3_0 547
|
||||
#define SLAVE_USB3_1 548
|
||||
#define SLAVE_VENUS_CFG 549
|
||||
#define SLAVE_VSENSE_CTRL_CFG 550
|
||||
#define SLAVE_A1NOC_SNOC 551
|
||||
#define SLAVE_A2NOC_SNOC 552
|
||||
#define SLAVE_GEM_NOC_CNOC 553
|
||||
#define SLAVE_SNOC_GEM_NOC_SF 554
|
||||
#define SLAVE_LLCC 555
|
||||
#define SLAVE_LPASS_GEM_NOC 556
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 557
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 558
|
||||
#define SLAVE_CDSP_MEM_NOC 559
|
||||
#define SLAVE_MEM_NOC_PCIE_SNOC 560
|
||||
#define SLAVE_ANOC_PCIE_GEM_NOC 561
|
||||
#define SLAVE_CNOC_CFG 562
|
||||
#define SLAVE_DDRSS_CFG 563
|
||||
#define SLAVE_CNOC_MNOC_HF_CFG 564
|
||||
#define SLAVE_CNOC_MNOC_SF_CFG 565
|
||||
#define SLAVE_PCIE_ANOC_CFG 566
|
||||
#define SLAVE_QUP_CORE_1 567
|
||||
#define SLAVE_QUP_CORE_2 568
|
||||
#define SLAVE_QUP_CORE_3 569
|
||||
#define SLAVE_BOOT_IMEM 570
|
||||
#define SLAVE_BOOT_IMEM_2 571
|
||||
#define SLAVE_IMEM 572
|
||||
#define SLAVE_SERVICE_CNOC 573
|
||||
#define SLAVE_SERVICE_MNOC_HF 574
|
||||
#define SLAVE_SERVICE_MNOC_SF 575
|
||||
#define SLAVE_SERVICES_LPASS_AML_NOC 576
|
||||
#define SLAVE_SERVICE_LPASS_AG_NOC 577
|
||||
#define SLAVE_SERVICE_PCIE_ANOC 578
|
||||
#define SLAVE_PCIE_0 579
|
||||
#define SLAVE_PCIE_2 580
|
||||
#define SLAVE_PCIE_1 581
|
||||
#define SLAVE_QDSS_STM 582
|
||||
#define SLAVE_TCU 583
|
||||
#define MASTER_LLCC_DISP 1000
|
||||
#define MASTER_MDP0_DISP 1001
|
||||
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
|
||||
|
||||
Loading…
Reference in New Issue
Block a user