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bindings: clock: qcom: Add support for clock IDs for volcano

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Add the clock handles for CAMCC/DISPCC/GCC/GPUCC/VIDEOCC, so
that the clients can request on the clock ids.

Change-Id: Id9f72c77d34e4aa48394c087282b748573cdc131
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
This commit is contained in:
Ajit Pandey 2023-09-12 00:09:25 +05:30
parent c5b2b7e279
commit 7555920df5
5 changed files with 465 additions and 0 deletions
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127
include/dt-bindings/clock/qcom,camcc-volcano.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_VOLCANO_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_VOLCANO_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL2_OUT_EVEN 6
#define CAM_CC_PLL3 7
#define CAM_CC_PLL3_OUT_EVEN 8
#define CAM_CC_PLL4 9
#define CAM_CC_PLL4_OUT_EVEN 10
#define CAM_CC_PLL5 11
#define CAM_CC_PLL5_OUT_EVEN 12
#define CAM_CC_PLL6 13
#define CAM_CC_PLL6_OUT_EVEN 14
#define CAM_CC_BPS_AHB_CLK 15
#define CAM_CC_BPS_AREG_CLK 16
#define CAM_CC_BPS_CLK 17
#define CAM_CC_BPS_CLK_SRC 18
#define CAM_CC_CAMNOC_ATB_CLK 19
#define CAM_CC_CAMNOC_AXI_CLK_SRC 20
#define CAM_CC_CAMNOC_AXI_HF_CLK 21
#define CAM_CC_CAMNOC_AXI_SF_CLK 22
#define CAM_CC_CAMNOC_NRT_AXI_CLK 23
#define CAM_CC_CAMNOC_RT_AXI_CLK 24
#define CAM_CC_CCI_0_CLK 25
#define CAM_CC_CCI_0_CLK_SRC 26
#define CAM_CC_CCI_1_CLK 27
#define CAM_CC_CCI_1_CLK_SRC 28
#define CAM_CC_CORE_AHB_CLK 29
#define CAM_CC_CPAS_AHB_CLK 30
#define CAM_CC_CPHY_RX_CLK_SRC 31
#define CAM_CC_CRE_AHB_CLK 32
#define CAM_CC_CRE_CLK 33
#define CAM_CC_CRE_CLK_SRC 34
#define CAM_CC_CSI0PHYTIMER_CLK 35
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 36
#define CAM_CC_CSI1PHYTIMER_CLK 37
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 38
#define CAM_CC_CSI2PHYTIMER_CLK 39
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 40
#define CAM_CC_CSI3PHYTIMER_CLK 41
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 42
#define CAM_CC_CSIPHY0_CLK 43
#define CAM_CC_CSIPHY1_CLK 44
#define CAM_CC_CSIPHY2_CLK 45
#define CAM_CC_CSIPHY3_CLK 46
#define CAM_CC_FAST_AHB_CLK_SRC 47
#define CAM_CC_GDSC_CLK 48
#define CAM_CC_ICP_ATB_CLK 49
#define CAM_CC_ICP_CLK 50
#define CAM_CC_ICP_CLK_SRC 51
#define CAM_CC_ICP_CTI_CLK 52
#define CAM_CC_ICP_TS_CLK 53
#define CAM_CC_MCLK0_CLK 54
#define CAM_CC_MCLK0_CLK_SRC 55
#define CAM_CC_MCLK1_CLK 56
#define CAM_CC_MCLK1_CLK_SRC 57
#define CAM_CC_MCLK2_CLK 58
#define CAM_CC_MCLK2_CLK_SRC 59
#define CAM_CC_MCLK3_CLK 60
#define CAM_CC_MCLK3_CLK_SRC 61
#define CAM_CC_MCLK4_CLK 62
#define CAM_CC_MCLK4_CLK_SRC 63
#define CAM_CC_OPE_0_AHB_CLK 64
#define CAM_CC_OPE_0_AREG_CLK 65
#define CAM_CC_OPE_0_CLK 66
#define CAM_CC_OPE_0_CLK_SRC 67
#define CAM_CC_SLEEP_CLK 68
#define CAM_CC_SLEEP_CLK_SRC 69
#define CAM_CC_SLOW_AHB_CLK_SRC 70
#define CAM_CC_SOC_AHB_CLK 71
#define CAM_CC_SYS_TMR_CLK 72
#define CAM_CC_TFE_0_AHB_CLK 73
#define CAM_CC_TFE_0_CLK 74
#define CAM_CC_TFE_0_CLK_SRC 75
#define CAM_CC_TFE_0_CPHY_RX_CLK 76
#define CAM_CC_TFE_0_CSID_CLK 77
#define CAM_CC_TFE_0_CSID_CLK_SRC 78
#define CAM_CC_TFE_1_AHB_CLK 79
#define CAM_CC_TFE_1_CLK 80
#define CAM_CC_TFE_1_CLK_SRC 81
#define CAM_CC_TFE_1_CPHY_RX_CLK 82
#define CAM_CC_TFE_1_CSID_CLK 83
#define CAM_CC_TFE_1_CSID_CLK_SRC 84
#define CAM_CC_TFE_2_AHB_CLK 85
#define CAM_CC_TFE_2_CLK 86
#define CAM_CC_TFE_2_CLK_SRC 87
#define CAM_CC_TFE_2_CPHY_RX_CLK 88
#define CAM_CC_TFE_2_CSID_CLK 89
#define CAM_CC_TFE_2_CSID_CLK_SRC 90
#define CAM_CC_TOP_SHIFT_CLK 91
#define CAM_CC_XO_CLK_SRC 92
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CAMSS_TOP_BCR 2
#define CAM_CC_CCI_0_BCR 3
#define CAM_CC_CCI_1_BCR 4
#define CAM_CC_CPAS_BCR 5
#define CAM_CC_CRE_BCR 6
#define CAM_CC_CSI0PHY_BCR 7
#define CAM_CC_CSI1PHY_BCR 8
#define CAM_CC_CSI2PHY_BCR 9
#define CAM_CC_CSI3PHY_BCR 10
#define CAM_CC_ICP_BCR 11
#define CAM_CC_MCLK0_BCR 12
#define CAM_CC_MCLK1_BCR 13
#define CAM_CC_MCLK2_BCR 14
#define CAM_CC_MCLK3_BCR 15
#define CAM_CC_MCLK4_BCR 16
#define CAM_CC_OPE_0_BCR 17
#define CAM_CC_TFE_0_BCR 18
#define CAM_CC_TFE_1_BCR 19
#define CAM_CC_TFE_2_BCR 20
#endif

56
include/dt-bindings/clock/qcom,dispcc-volcano.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_VOLCANO_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_VOLCANO_H
/* DISP_CC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_MDSS_ACCU_CLK 1
#define DISP_CC_MDSS_AHB1_CLK 2
#define DISP_CC_MDSS_AHB_CLK 3
#define DISP_CC_MDSS_AHB_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_CLK 5
#define DISP_CC_MDSS_BYTE0_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
#define DISP_CC_MDSS_BYTE0_INTF_CLK 8
#define DISP_CC_MDSS_DPTX0_AUX_CLK 9
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11
#define DISP_CC_MDSS_DPTX0_LINK_CLK 12
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20
#define DISP_CC_MDSS_ESC0_CLK 21
#define DISP_CC_MDSS_ESC0_CLK_SRC 22
#define DISP_CC_MDSS_MDP1_CLK 23
#define DISP_CC_MDSS_MDP_CLK 24
#define DISP_CC_MDSS_MDP_CLK_SRC 25
#define DISP_CC_MDSS_MDP_LUT1_CLK 26
#define DISP_CC_MDSS_MDP_LUT_CLK 27
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28
#define DISP_CC_MDSS_PCLK0_CLK 29
#define DISP_CC_MDSS_PCLK0_CLK_SRC 30
#define DISP_CC_MDSS_RSCC_AHB_CLK 31
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 32
#define DISP_CC_MDSS_VSYNC1_CLK 33
#define DISP_CC_MDSS_VSYNC_CLK 34
#define DISP_CC_MDSS_VSYNC_CLK_SRC 35
#define DISP_CC_SLEEP_CLK 36
#define DISP_CC_SLEEP_CLK_SRC 37
#define DISP_CC_XO_CLK 38
#define DISP_CC_XO_CLK_SRC 39
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

199
include/dt-bindings/clock/qcom,gcc-volcano.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_VOLCANO_H
#define _DT_BINDINGS_CLK_QCOM_GCC_VOLCANO_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL2 2
#define GCC_GPLL4 3
#define GCC_GPLL6 4
#define GCC_GPLL7 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 7
#define GCC_AGGRE_UFS_PHY_AXI_CLK 8
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10
#define GCC_BOOT_ROM_AHB_CLK 11
#define GCC_CAMERA_AHB_CLK 12
#define GCC_CAMERA_HF_AXI_CLK 13
#define GCC_CAMERA_HF_XO_CLK 14
#define GCC_CAMERA_SF_AXI_CLK 15
#define GCC_CAMERA_SF_XO_CLK 16
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 17
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 18
#define GCC_CNOC_PCIE_SF_AXI_CLK 19
#define GCC_DDRSS_GPU_AXI_CLK 20
#define GCC_DDRSS_PCIE_SF_QTB_CLK 21
#define GCC_DISP_AHB_CLK 22
#define GCC_DISP_GPLL0_DIV_CLK_SRC 23
#define GCC_DISP_HF_AXI_CLK 24
#define GCC_DISP_XO_CLK 25
#define GCC_GP1_CLK 26
#define GCC_GP1_CLK_SRC 27
#define GCC_GP2_CLK 28
#define GCC_GP2_CLK_SRC 29
#define GCC_GP3_CLK 30
#define GCC_GP3_CLK_SRC 31
#define GCC_GPU_CFG_AHB_CLK 32
#define GCC_GPU_GPLL0_CLK_SRC 33
#define GCC_GPU_GPLL0_DIV_CLK_SRC 34
#define GCC_GPU_MEMNOC_GFX_CLK 35
#define GCC_GPU_SNOC_DVM_GFX_CLK 36
#define GCC_PCIE_0_AUX_CLK 37
#define GCC_PCIE_0_AUX_CLK_SRC 38
#define GCC_PCIE_0_CFG_AHB_CLK 39
#define GCC_PCIE_0_MSTR_AXI_CLK 40
#define GCC_PCIE_0_PHY_RCHNG_CLK 41
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
#define GCC_PCIE_0_PIPE_CLK 43
#define GCC_PCIE_0_PIPE_CLK_SRC 44
#define GCC_PCIE_0_PIPE_DIV2_CLK 45
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PCIE_1_AUX_CLK 49
#define GCC_PCIE_1_AUX_CLK_SRC 50
#define GCC_PCIE_1_CFG_AHB_CLK 51
#define GCC_PCIE_1_MSTR_AXI_CLK 52
#define GCC_PCIE_1_PHY_RCHNG_CLK 53
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54
#define GCC_PCIE_1_PIPE_CLK 55
#define GCC_PCIE_1_PIPE_CLK_SRC 56
#define GCC_PCIE_1_PIPE_DIV2_CLK 57
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 58
#define GCC_PCIE_1_SLV_AXI_CLK 59
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 60
#define GCC_PCIE_RSCC_CFG_AHB_CLK 61
#define GCC_PCIE_RSCC_XO_CLK 62
#define GCC_PDM2_CLK 63
#define GCC_PDM2_CLK_SRC 64
#define GCC_PDM_AHB_CLK 65
#define GCC_PDM_XO4_CLK 66
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 67
#define GCC_QMIP_CAMERA_RT_AHB_CLK 68
#define GCC_QMIP_DISP_AHB_CLK 69
#define GCC_QMIP_GPU_AHB_CLK 70
#define GCC_QMIP_PCIE_AHB_CLK 71
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 72
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 73
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 74
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 75
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 76
#define GCC_QUPV3_WRAP0_CORE_CLK 77
#define GCC_QUPV3_WRAP0_QSPI_REF_CLK 78
#define GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC 79
#define GCC_QUPV3_WRAP0_S0_CLK 80
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 81
#define GCC_QUPV3_WRAP0_S1_CLK 82
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 83
#define GCC_QUPV3_WRAP0_S2_CLK 84
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 85
#define GCC_QUPV3_WRAP0_S3_CLK 86
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 87
#define GCC_QUPV3_WRAP0_S4_CLK 88
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 89
#define GCC_QUPV3_WRAP0_S5_CLK 90
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 91
#define GCC_QUPV3_WRAP0_S6_CLK 92
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 93
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 94
#define GCC_QUPV3_WRAP1_CORE_CLK 95
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 96
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S0_CLK 98
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S1_CLK 100
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S2_CLK 102
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 103
#define GCC_QUPV3_WRAP1_S3_CLK 104
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 105
#define GCC_QUPV3_WRAP1_S4_CLK 106
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 107
#define GCC_QUPV3_WRAP1_S5_CLK 108
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 109
#define GCC_QUPV3_WRAP1_S6_CLK 110
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 111
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 112
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 113
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 114
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 115
#define GCC_SDCC1_AHB_CLK 116
#define GCC_SDCC1_APPS_CLK 117
#define GCC_SDCC1_APPS_CLK_SRC 118
#define GCC_SDCC1_ICE_CORE_CLK 119
#define GCC_SDCC1_ICE_CORE_CLK_SRC 120
#define GCC_SDCC2_AHB_CLK 121
#define GCC_SDCC2_APPS_CLK 122
#define GCC_SDCC2_APPS_CLK_SRC 123
#define GCC_UFS_PHY_AHB_CLK 124
#define GCC_UFS_PHY_AXI_CLK 125
#define GCC_UFS_PHY_AXI_CLK_SRC 126
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 127
#define GCC_UFS_PHY_ICE_CORE_CLK 128
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 130
#define GCC_UFS_PHY_PHY_AUX_CLK 131
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 132
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 133
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 134
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 135
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 136
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 137
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 139
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 140
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 141
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 142
#define GCC_USB30_PRIM_ATB_CLK 143
#define GCC_USB30_PRIM_MASTER_CLK 144
#define GCC_USB30_PRIM_MASTER_CLK_SRC 145
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 146
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 147
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 148
#define GCC_USB30_PRIM_SLEEP_CLK 149
#define GCC_USB3_PRIM_PHY_AUX_CLK 150
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 151
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 152
#define GCC_USB3_PRIM_PHY_PIPE_CLK 153
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 154
#define GCC_VIDEO_AHB_CLK 155
#define GCC_VIDEO_AXI0_CLK 156
#define GCC_VIDEO_XO_CLK 157
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_PCIE_0_BCR 3
#define GCC_PCIE_0_LINK_DOWN_BCR 4
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_PHY_BCR 6
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_1_BCR 8
#define GCC_PCIE_1_LINK_DOWN_BCR 9
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_PHY_BCR 11
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_RSCC_BCR 13
#define GCC_PDM_BCR 14
#define GCC_QUPV3_WRAPPER_0_BCR 15
#define GCC_QUPV3_WRAPPER_1_BCR 16
#define GCC_QUSB2PHY_PRIM_BCR 17
#define GCC_QUSB2PHY_SEC_BCR 18
#define GCC_SDCC1_BCR 19
#define GCC_SDCC2_BCR 20
#define GCC_UFS_PHY_BCR 21
#define GCC_USB30_PRIM_BCR 22
#define GCC_USB3_DP_PHY_PRIM_BCR 23
#define GCC_USB3_PHY_PRIM_BCR 24
#define GCC_USB3PHY_PHY_PRIM_BCR 25
#define GCC_VIDEO_AXI0_CLK_ARES 26
#define GCC_VIDEO_BCR 27
#endif

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include/dt-bindings/clock/qcom,gpucc-volcano.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_VOLCANO_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_VOLCANO_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL0_OUT_EVEN 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CX_ACCU_SHIFT_CLK 4
#define GPU_CC_CX_FF_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_DEMET_CLK 9
#define GPU_CC_DEMET_DIV_CLK_SRC 10
#define GPU_CC_DPM_CLK 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_FREQ_MEASURE_CLK 13
#define GPU_CC_GMU_CLK_SRC 14
#define GPU_CC_GX_ACCU_SHIFT_CLK 15
#define GPU_CC_GX_ACD_AHB_FF_CLK 16
#define GPU_CC_GX_AHB_FF_CLK 17
#define GPU_CC_GX_GMU_CLK 18
#define GPU_CC_GX_RCG_AHB_FF_CLK 19
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 20
#define GPU_CC_HUB_AON_CLK 21
#define GPU_CC_HUB_CLK_SRC 22
#define GPU_CC_HUB_CX_INT_CLK 23
#define GPU_CC_HUB_DIV_CLK_SRC 24
#define GPU_CC_MEMNOC_GFX_CLK 25
#define GPU_CC_RSCC_HUB_AON_CLK 26
#define GPU_CC_RSCC_XO_AON_CLK 27
#define GPU_CC_SLEEP_CLK 28
#define GPU_CC_XO_CLK_SRC 29
#define GPU_CC_XO_DIV_CLK_SRC 30
/* GPU_CC resets */
#define GPU_CC_CB_BCR 0
#define GPU_CC_CX_BCR 1
#define GPU_CC_FAST_HUB_BCR 2
#define GPU_CC_FF_BCR 3
#define GPU_CC_GMU_BCR 4
#define GPU_CC_GX_BCR 5
#define GPU_CC_RBCPR_BCR 6
#define GPU_CC_XO_BCR 7
#endif

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include/dt-bindings/clock/qcom,videocc-volcano.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_VOLCANO_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_VOLCANO_H
/* VIDEO_CC clocks */
#define VIDEO_CC_PLL0 0
#define VIDEO_CC_AHB_CLK 1
#define VIDEO_CC_AHB_CLK_SRC 2
#define VIDEO_CC_MVS0_CLK 3
#define VIDEO_CC_MVS0_CLK_SRC 4
#define VIDEO_CC_MVS0_DIV_CLK_SRC 5
#define VIDEO_CC_MVS0_SHIFT_CLK 6
#define VIDEO_CC_MVS0C_CLK 7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define VIDEO_CC_MVS0C_SHIFT_CLK 9
#define VIDEO_CC_SLEEP_CLK 10
#define VIDEO_CC_SLEEP_CLK_SRC 11
#define VIDEO_CC_XO_CLK 12
#define VIDEO_CC_XO_CLK_SRC 13
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_CLK_ARES 2
#define VIDEO_CC_MVS0C_BCR 3
#endif