Change is to update the de-emphasis value of NTN3
via i2c register writes to resolve link failure
issues seen on MBB platforms.
Change-Id: If90e5efc19691a14c3d5f12af78df9ff5c2b2a25
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
NTN3 switch requires register access over i2c when the PCIe link
is not up. Add i2c control interface for an i2c client driver.
This i2c control interface registers with an i2c client driver
and provides client specific callbacks for read, write, reset
and register dump operations.i2c control interface can support
one i2c client per root port.
Change-Id: I9e5f91cab4fd2bb2c6274ad0317fad4279db6958
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
Unlock the recovery_lock in case of return in failure
in msm_pcie_pm_resume_noirq.
Change-Id: I6b71653bf64571273f443d26e49dba62027d715e
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
As per PCIE phy hardware programming guide all the clocks are
to be parked low before parking the phy in low power down mode.
As we need ahb clk enabled to access registers disable all clocks
except ahb clock and do the phy configurations and then disable
ahb clock in suspend path and do vice versa in resume path.
Change-Id: I4710cdea1a2be15bb45012dcbbe009117210d7f8
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Without disabling controller GDSC, XO shutdown is not being achieved.
When GDSC is turned off, it will reset controller and it can assert
CLKREQ GPIO. With assertion of CLKREQ gpio, endpoint tries to bring
link back to L0, but since all clocks are turned off on host, this
can result in link down.
So, release the control of CLKREQ gpio also from controller by
overriding it in suspend ops.
Change-Id: I4ba54c8b23487400bc19d1c3783bfe45f63980ed
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Update icc bw voting after the link is up based upon link speed and
width if there is no client based bw voting.
If there is already client based voting, vote for minimal bandwidth
which is needed to bring the PCIe link up. As client is already voting
based up on their requirement, if we vote based upon speed and width
we may end up voting for more bandwidth which may result in high power
consumption.
Change-Id: Ie0647530dddbe7493dc0e6d854d553c0b5c536ac
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Few PCIe endpoints like NVMe are always expecting the device
to be in D0 state and the link to be active (or in l1ss) all the
time (including in S3 state). Some NVMe endpoints are treating
link down as power cycle, So turning off the link during S3 can
reduce life span of the NVMe.
For that reason adding apss-based l1ss-sleep support. With this,
all the PCIe resources can be turned off after link has entered
into L1ss in the suspend path.
This meets NVMe requirements and also at the same time lets the
system go to XO shutdown.
Change-Id: I0d28567d37c1a4cfbfdc9294a132078b5c53e10d
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Enable WALT scheduler on niobe perf builds and insmod it early
during first stage.
Change-Id: I49253543449c0e11aabf5dc23b627eeec9bf9234
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
Volcano UFS PHY is reused from crow, hence Enable
CONFIG_PHY_QCOM_UFS_V4_CROW to enable ufs-phy driver
for volcano SoCs.
Also add UFS PHY module in modules.list.msm.pineapple
so that the module is loaded automatically from the
first stage RAM disk image during Linux kernel boot up.
Change-Id: I2774b710edc1e36823da41d8a577e7c38e4e3632
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Enable F_FS IPC logging and EHSET_TEST_FIXTURE configs on pitti.
Change-Id: Ie3f2558c6a763d3b2c53bbfff151d384cbb7281b
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Latest SNPS controller has implementation change in PM_LINKST_IN_L2,
hence status not reflecting in current register. H/W CR for the same
is QCTDD11307476.
Replace the PM_STTS register in sequence with PM_STTS_1 for checking
L2/3 entry.
PCIE_PARF_PM_STTS_1[CURNT_STATE]
0 : L0
1 : L0s
2 : L1
3 : L2
4 : Undefined
Poll PCIE_PARF_PM_STTS_1[CURNT_STATE] for 0x3 value to confirm L2 entry.
Since this register is present across target, should be safe to use it
across targets.
Change-Id: Ia339f0e47ca7b1ff12c14b4349ba7933dda6b241
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Enable memshare driver compilation necessary for
allocation of memory for the clients requesting.
Change-Id: I1512a69abb0599e82b1bd8a0d4ef1ba01ec31025
Signed-off-by: Fenil Panwala <quic_fpanwala@quicinc.com>
Out of tree (OOT) modules have a requirement to compile differently
for lunch target in Android builds but still use base target's
msm-kernel bazel package.
- How get_all_lunch_target_base_target_variants is used?
By calling this function from tech pack bazel file, It returns tuple of
(lunch_target, base_target, variant). This is useful to define a bazel
package sepcific to that lunch target
<base_target>_<variant>_<lunch_target>
- How build_module.sh calls this package to run in bazel?
When the script queries for the applicable packages under a folder,
it will query for <base_t>_<variant>_<lunch_t>. This regex will be
passed by individual OOT module's Makefile using
LOCAL_MODULE_DDK_SUBTARGET_REGEX
Syntax:
ifeq ($(TARGET_BOARD_PLATFORM), lunch_target)
LOCAL_MODULE_DDK_SUBTARGET_REGEX := "lunch_target_tech_regex.*"
endif
Change-Id: Id0b79292e9ef9a7ec1562ff6f48e0ba7c131c420
Signed-off-by: Auditya Bhattaram <quic_audityab@quicinc.com>
Enable show resume IRQs driver to log wake up interrupts bringing the
SoC out of low power mode for debugging.
Change-Id: I3f9b620c9e8527abfbbdd032419d4ebe677f122b
Signed-off-by: Raghavendra Kakarla <quic_rkakarla@quicinc.com>
Thread1: Thread2:
write_lock(&ctx->ctx_lock);
list_add_tail(&vchan->node,
&ctx->vchannels);
ctx->vcnt++;
write_unlock(&ctx->ctx_lock);
hab_vchan_close();
*vcid = vchan->id;
------------------------------------------------------
vchan object will be freed by hab_vchan_close(), so
*vcid = vchan->id will cause Use-Afer-Free issue.
Change-Id: I8fb5e6a619914d5843564c3e36b0ba16f48953cf
Signed-off-by: Deyan Wang <quic_deyawang@quicinc.com>
Enable SDExpress platform driver configs for niobe.
Change-Id: Ia11ff7c95b694c91a7fecbbc45ed5bdfc2530422
Signed-off-by: Pradeep P V K <quic_pragalla@quicinc.com>
In some situations, it is observed that during a faulty connect
where enumeration has failed, the controller goes into a bad state
where it is not able to generate any events. As a result when a plug
out happens in this scenario, the disconnect event isn't generated
by the controller and after the 2 second timeout, we exit the start
peripheral call setting WAIT_FOR_LPM bit. But since the connected
flag was never set to false, the idle/suspend routines for core
fail and the wrapper's suspend routine too is not called. This
instability causes further Plug-In from enumerating the device and
further plug-outs to enter LPM.
As per the debug analysis done so far, this is due to either AXI
response hang or the TBT command (internal)/response hang. While
debug is in progress, SNPS suggested restarting the device mode.
Fix this by forcing disconnect during faulty plug-out and fix the
gadget connect during next plug-in. Also since the user is free to
do a composition switch after faulty plug-out and before next plug
in, ensure to check whether udc is binded or not to avoid duplicate
calls to gadget_connect.
Change-Id: Ica53db16dc6d51bf652679ecfa967347c6c5f384
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Add a new platform driver support to detect and
power control for the new sdexpress cards.
[quic_mapa: modify below from change 67c2aa7
- replace mdelay() with usleep_range() in msm_sdexpress.c:749.
- Prefer "GPL" over "GPL v2"].
Change-Id: If042c7e9cc12d15c16856e2cda8abdec52c920df
Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Pradeep P V K <quic_pragalla@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
