Merge "pci: msm: Update the L2_entry status polling logic"
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c22f2506bb
@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
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/* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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@ -107,6 +107,12 @@
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#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1 (0xc84)
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#define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2 (0xc88)
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#define PCIE20_PARF_PM_STTS_1 (0x28)
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#define PM_STATE_L0 0
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#define PM_STATE_L0s 1
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#define PM_STATE_L1 2
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#define PM_STATE_L2 3
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#define PCIE_LINK_PM_STATE(val) ((val & (7 << 7)) >> 7)
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#define PCIE_LINK_IN_L2_STATE(val) ((PCIE_LINK_PM_STATE(val)) == PM_STATE_L2)
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#define PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS (0x4D0)
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#define PCIE20_PARF_L1SS_SLEEP_MODE_HANDLER_CFG (0x4D4)
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#define PCIE20_PARF_CORE_ERRORS (0x3C0)
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@ -9305,14 +9311,14 @@ static int msm_pcie_pm_suspend(struct pci_dev *dev,
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PCIE_DBG(pcie_dev, "RC%d: PME_TURNOFF_MSG is sent out\n",
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pcie_dev->rc_idx);
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ret_l23 = readl_poll_timeout((pcie_dev->parf
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+ PCIE20_PARF_PM_STTS), val, (val & BIT(5)), 10000,
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pcie_dev->l23_rdy_poll_timeout);
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ret_l23 = readl_poll_timeout((pcie_dev->parf + PCIE20_PARF_PM_STTS_1),
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val, PCIE_LINK_IN_L2_STATE(val),
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9000, pcie_dev->l23_rdy_poll_timeout);
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/* check L23_Ready */
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PCIE_DBG(pcie_dev, "RC%d: PCIE20_PARF_PM_STTS is 0x%x.\n",
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PCIE_DBG(pcie_dev, "RC%d: PCIE20_PARF_PM_STTS_1 is 0x%x.\n",
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pcie_dev->rc_idx,
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readl_relaxed(pcie_dev->parf + PCIE20_PARF_PM_STTS));
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readl_relaxed(pcie_dev->parf + PCIE20_PARF_PM_STTS_1));
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if (!ret_l23)
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PCIE_DBG(pcie_dev, "RC%d: PM_Enter_L23 is received\n",
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pcie_dev->rc_idx);
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