Dinh Nguyen 40ae25505f net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
 - The emac PHY setup bits are in separate registers.
 - The PTP reference clock select mask is different.
 - The register to enable the emac signal from FPGA is different.

Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-06-06 14:21:06 -07:00
2019-05-30 19:58:59 -07:00
2019-03-06 14:18:59 -08:00
2019-03-10 17:48:21 -07:00
2019-06-02 18:16:23 -07:00
2019-05-26 16:49:19 -07:00

Linux kernel
============

There are several guides for kernel developers and users. These guides can
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In order to build the documentation, use ``make htmldocs`` or
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There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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