android/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

msm: ep-pcie: Update logic to access TCSR registers

Browse Source 
TCSR registers will not be available in all targets.
Update logic such that TCSR registers will be accessed
only if available.

Remove unnecessary header files.

Change-Id: If1d2e58281b2924dbdc078baa78c2d3274384445
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
This commit is contained in:
Rama Krishna Phani A 2021-07-29 17:22:22 +05:30 committed by Sriharsha Allenki
parent 4fba626ad2
commit cf0163dfa4
1 changed files with 12 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/platform/msm/ep_pcie/ep_pcie_core.c
View File

@ -27,7 +27,6 @@
#include <linux/interconnect.h>
#include "ep_pcie_com.h"
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#define PCIE_MHI_STATUS(n) ((n) + 0x148)
@ -667,8 +666,12 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 0);
if (!dev->tcsr_not_supported) {
EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 0);
}
}
if (dev->active_config) {
@ -2047,10 +2050,12 @@ int ep_pcie_core_disable_endpoint(void)
EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE during disable:0x%x\n",
dev->rev, (val >> 0xC) & 0x3f);
EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 1);
if (!dev->tcsr_not_supported) {
EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 1);
}
ep_pcie_pipe_clk_deinit(dev);
ep_pcie_clk_deinit(dev);