From cf0163dfa4ac53fa01a26ad1e429be64234b805f Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Thu, 29 Jul 2021 17:22:22 +0530 Subject: [PATCH] msm: ep-pcie: Update logic to access TCSR registers TCSR registers will not be available in all targets. Update logic such that TCSR registers will be accessed only if available. Remove unnecessary header files. Change-Id: If1d2e58281b2924dbdc078baa78c2d3274384445 Signed-off-by: Rama Krishna Phani A --- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 3d6d716b3065..edfa31ef13c6 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -27,7 +27,6 @@ #include #include "ep_pcie_com.h" -#include #include #define PCIE_MHI_STATUS(n) ((n) + 0x148) @@ -667,8 +666,12 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n", dev->rev); - ep_pcie_write_reg_field(dev->tcsr_perst_en, - TCSR_PCIE_RST_SEPARATION, BIT(5), 0); + if (!dev->tcsr_not_supported) { + EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n", + dev->rev); + ep_pcie_write_reg_field(dev->tcsr_perst_en, + TCSR_PCIE_RST_SEPARATION, BIT(5), 0); + } } if (dev->active_config) { @@ -2047,10 +2050,12 @@ int ep_pcie_core_disable_endpoint(void) EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE during disable:0x%x\n", dev->rev, (val >> 0xC) & 0x3f); - EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n", - dev->rev); - ep_pcie_write_reg_field(dev->tcsr_perst_en, - TCSR_PCIE_RST_SEPARATION, BIT(5), 1); + if (!dev->tcsr_not_supported) { + EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n", + dev->rev); + ep_pcie_write_reg_field(dev->tcsr_perst_en, + TCSR_PCIE_RST_SEPARATION, BIT(5), 1); + } ep_pcie_pipe_clk_deinit(dev); ep_pcie_clk_deinit(dev);