MIPS: Remove GCC_IMM_ASM & GCC_REG_ACCUM macros
asm/compiler.h defined GCC_IMM_ASM & GCC_REG_ACCUM macros, both of which are defined differently for GCC pre-3.4 or GCC 3.4 & higher. We only support building with GCC 4.6 & higher since commit cafa0010cd51 ("Raise the minimum required gcc version to 4.6"), which makes the pre-3.4 definition dead code. Rather than leave the macro definitions around, inline the GCC 3.4 & higher definitions into the single file that uses them & remove the macros entirely. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21000/ Cc: linux-mips@linux-mips.org
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@ -43,14 +43,6 @@
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#undef barrier_before_unreachable
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#define barrier_before_unreachable() asm volatile(".insn")
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#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
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#define GCC_IMM_ASM() "n"
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#define GCC_REG_ACCUM "$0"
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#else
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#define GCC_IMM_ASM() "rn"
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#define GCC_REG_ACCUM "accum"
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#endif
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#ifdef CONFIG_CPU_MIPSR6
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/* All MIPS R6 toolchains support the ZC constrain */
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#define GCC_OFF_SMALL_ASM() "ZC"
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@ -39,7 +39,7 @@ static inline void align_mod(const int align, const int mod)
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".endr\n\t"
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".set pop"
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:
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: GCC_IMM_ASM() (align), GCC_IMM_ASM() (mod));
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: "n"(align), "n"(mod));
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}
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static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
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@ -92,7 +92,7 @@ static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
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".set pop"
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: "=&r" (lv1), "=r" (lw)
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: "r" (m1), "r" (m2), "r" (s), "I" (0)
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: "hi", "lo", GCC_REG_ACCUM);
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: "hi", "lo", "$0");
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/* We have to use single integers for m1 and m2 and a double
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* one for p to be sure the mulsidi3 gcc's RTL multiplication
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* instruction has the workaround applied. Older versions of
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