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clk: tegra: Fix cclk_lp divisor register

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According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Michał Mirosław
2017-09-19 04:48:10 +02:00
committed by Thierry Reding
parent d80a32fe98
commit 54eff2264d
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/tegra/clk-tegra30.c
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@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void)
* U71 divider of cclk_lp.
*/
clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
clk_base + SUPER_CCLKG_DIVIDER, 0,
clk_base + SUPER_CCLKLP_DIVIDER, 0,
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);