Amlogic clock updates for v5.6:
* Add meson8b DDR clock controller * Add input clocks to meson8b controllers * Fix meson8b mali clock update using the glitch free mux * Fix pll driver division by zero init -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl4Ynz8ACgkQ5vwPHDfy 2oVDvA/+PUQpHkHGdGrtcUPyr0fIdN40QTCCaxLLTN9MJ9RAn5KfoPWx6E8Txjps RhBu7L61J1eOVwQywzPdd82+1o2O/75H2gx6iIi0dUc+0cAlsskJlifMHRxyLeqo cByv6g5AtaVgxUCyZVqtYljNMUHUGh5FagFvpwNgIihI/3kxqwvuO00wCgH/vZoK lOHwjEvdYXqFpwSlcDd5CN3BthUnusR+lp83DhFdf2JnpvBkJJYdmK6YPCRYeFJc RCxeongMeIgyTgxLU8TBDl+jWsOGl9vgmj+HJ2D/+XLoc+gE072PvMw5feR+NZwr lwbW56y8Wm9ibvXVzXazETOJLORoWJ3Isy7C2NQ6olorqbEvdHctpqC2Idp7Vaib A1fpyWxs/9PPi1MPSvudj1ro54fEs31frI+/vRwQwwIJ0b8ZsP2BFG1QP2NgYSEA qxRUpz8AQHI16HtWNa+RTDY6Sv2MxI5S5UZLRCSQtJbvnNW3XAwwRlEWcrvjETr7 /7R6+Tu73OmdJr9A19+cxxGMwFdIt01ZWmKEhslQxf8jod95eHSUEv7+gobMlqga dIVaO+h8Vf4S4Vq1s7OUADITWfOoEFWUFFlSXaey0RTO0QteN4YVvn9ffuMTg0VI WVg6msr5tfqmX+39TmHhsmEIY+NgBT7688ugxXcbnJx6eIe5Ftc= =kcfQ -----END PGP SIGNATURE----- Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Add meson8b DDR clock controller - Add input clocks to meson8b controllers - Fix meson8b mali clock update using the glitch free mux - Fix pll driver division by zero init * tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson: clk: clarify that clk_set_rate() does updates from top to bottom clk: meson: meson8b: make the CCF use the glitch-free mali mux clk: meson: pll: Fix by 0 division in __pll_params_to_rate() clk: meson: g12a: fix missing uart2 in regmap table clk: meson: meson8b: use of_clk_hw_register to register the clocks clk: meson: meson8b: don't register the XTAL clock when provided via OF clk: meson: meson8b: change references to the XTAL clock to use [fw_]name clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller dt-bindings: clock: meson8b: add the clock inputs dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
This commit is contained in:
Stephen Boyd
@ -0,0 +1,50 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic DDR Clock Controller Device Tree Bindings
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maintainers:
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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properties:
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compatible:
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enum:
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- amlogic,meson8-ddr-clkc
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- amlogic,meson8b-ddr-clkc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: xtal
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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ddr_clkc: clock-controller@400 {
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compatible = "amlogic,meson8-ddr-clkc";
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reg = <0x400 0x20>;
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clocks = <&xtal>;
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clock-names = "xtal";
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#clock-cells = <1>;
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};
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...
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@ -11,6 +11,11 @@ Required Properties:
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- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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- clocks: list of clock phandles, one for each entry in clock-names
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- clock-names: should contain the following:
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* "xtal": the 24MHz system oscillator
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* "ddr_pll": the DDR PLL clock
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* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
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Parent node should have the following properties :
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- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
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@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
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@ -77,6 +77,15 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned int m, n, frac;
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n = meson_parm_read(clk->map, &pll->n);
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/*
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* On some HW, N is set to zero on init. This value is invalid as
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* it would result in a division by zero. The rate can't be
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* calculated in this case
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*/
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if (n == 0)
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return 0;
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m = meson_parm_read(clk->map, &pll->m);
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frac = MESON_PARM_APPLICABLE(&pll->frac) ?
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@ -4692,6 +4692,7 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
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&g12a_bt656,
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&g12a_usb1_to_ddr,
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&g12a_mmc_pclk,
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&g12a_uart2,
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&g12a_vpu_intr,
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&g12a_gic,
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&g12a_sd_emmc_a_clk0,
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149
drivers/clk/meson/meson8-ddr.c
Normal file
149
drivers/clk/meson/meson8-ddr.c
Normal file
@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson8 DDR clock controller
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*
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* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#define AM_DDR_PLL_CNTL 0x00
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#define AM_DDR_PLL_CNTL1 0x04
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#define AM_DDR_PLL_CNTL2 0x08
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#define AM_DDR_PLL_CNTL3 0x0c
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#define AM_DDR_PLL_CNTL4 0x10
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#define AM_DDR_PLL_STS 0x14
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#define DDR_CLK_CNTL 0x18
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#define DDR_CLK_STS 0x1c
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static struct clk_regmap meson8_ddr_pll_dco = {
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.data = &(struct meson_clk_pll_data){
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.en = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 30,
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.width = 1,
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},
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.m = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 9,
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.width = 5,
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},
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.l = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 29,
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.width = 1,
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},
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},
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.hw.init = &(struct clk_init_data){
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.name = "ddr_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap meson8_ddr_pll = {
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.data = &(struct clk_regmap_div_data){
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.offset = AM_DDR_PLL_CNTL,
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.shift = 16,
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.width = 2,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ddr_pll",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8_ddr_pll_dco.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
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.hws = {
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[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
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[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
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},
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.num = 2,
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};
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static struct clk_regmap *const meson8_ddr_clk_regmaps[] = {
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&meson8_ddr_pll_dco,
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&meson8_ddr_pll,
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};
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static const struct regmap_config meson8_ddr_clkc_regmap_config = {
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = DDR_CLK_STS,
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};
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static int meson8_ddr_clkc_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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void __iomem *base;
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struct clk_hw *hw;
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int ret, i;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&meson8_ddr_clkc_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Populate regmap */
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for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++)
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meson8_ddr_clk_regmaps[i]->map = regmap;
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/* Register all clks */
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for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
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hw = meson8_ddr_clk_hw_onecell_data.hws[i];
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ret = devm_clk_hw_register(&pdev->dev, hw);
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if (ret) {
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dev_err(&pdev->dev, "Clock registration failed\n");
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return ret;
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}
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}
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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&meson8_ddr_clk_hw_onecell_data);
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}
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static const struct of_device_id meson8_ddr_clkc_match_table[] = {
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{ .compatible = "amlogic,meson8-ddr-clkc" },
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{ .compatible = "amlogic,meson8b-ddr-clkc" },
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{ /* sentinel */ }
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};
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static struct platform_driver meson8_ddr_clkc_driver = {
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.probe = meson8_ddr_clkc_probe,
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.driver = {
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.name = "meson8-ddr-clkc",
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.of_match_table = meson8_ddr_clkc_match_table,
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},
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};
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builtin_platform_driver(meson8_ddr_clkc_driver);
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@ -97,8 +97,10 @@ static struct clk_regmap meson8b_fixed_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "fixed_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8b_xtal.hw
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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.name = "xtal",
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.index = -1,
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},
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.num_parents = 1,
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},
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@ -162,8 +164,10 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
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/* sometimes also called "HPLL" or "HPLL PLL" */
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.name = "hdmi_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8b_xtal.hw
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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.name = "xtal",
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.index = -1,
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},
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.num_parents = 1,
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},
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@ -237,8 +241,10 @@ static struct clk_regmap meson8b_sys_pll_dco = {
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8b_xtal.hw
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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.name = "xtal",
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.index = -1,
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},
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.num_parents = 1,
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},
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@ -631,9 +637,9 @@ static struct clk_regmap meson8b_cpu_in_sel = {
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.hw.init = &(struct clk_init_data){
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.name = "cpu_in_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8b_xtal.hw,
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&meson8b_sys_pll.hw,
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.parent_data = (const struct clk_parent_data[]) {
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{ .fw_name = "xtal", .name = "xtal", .index = -1, },
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{ .hw = &meson8b_sys_pll.hw, },
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},
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.num_parents = 2,
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.flags = (CLK_SET_RATE_PARENT |
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@ -736,9 +742,9 @@ static struct clk_regmap meson8b_cpu_clk = {
|
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.hw.init = &(struct clk_init_data){
|
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.name = "cpu_clk",
|
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.ops = &clk_regmap_mux_ops,
|
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.parent_hws = (const struct clk_hw *[]) {
|
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&meson8b_xtal.hw,
|
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&meson8b_cpu_scale_out_sel.hw,
|
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.parent_data = (const struct clk_parent_data[]) {
|
||||
{ .fw_name = "xtal", .name = "xtal", .index = -1, },
|
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{ .hw = &meson8b_cpu_scale_out_sel.hw, },
|
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},
|
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.num_parents = 2,
|
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.flags = (CLK_SET_RATE_PARENT |
|
||||
@ -758,12 +764,12 @@ static struct clk_regmap meson8b_nand_clk_sel = {
|
||||
.name = "nand_clk_sel",
|
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.ops = &clk_regmap_mux_ops,
|
||||
/* FIXME all other parents are unknown: */
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_fclk_div4.hw,
|
||||
&meson8b_fclk_div3.hw,
|
||||
&meson8b_fclk_div5.hw,
|
||||
&meson8b_fclk_div7.hw,
|
||||
&meson8b_xtal.hw,
|
||||
.parent_data = (const struct clk_parent_data[]) {
|
||||
{ .hw = &meson8b_fclk_div4.hw, },
|
||||
{ .hw = &meson8b_fclk_div3.hw, },
|
||||
{ .hw = &meson8b_fclk_div5.hw, },
|
||||
{ .hw = &meson8b_fclk_div7.hw, },
|
||||
{ .fw_name = "xtal", .name = "xtal", .index = -1, },
|
||||
},
|
||||
.num_parents = 5,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1721,8 +1727,10 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
|
||||
.name = "hdmi_sys_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
/* FIXME: all other parents are unknown */
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_xtal.hw
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.fw_name = "xtal",
|
||||
.name = "xtal",
|
||||
.index = -1,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
@ -1764,17 +1772,20 @@ static struct clk_regmap meson8b_hdmi_sys = {
|
||||
|
||||
/*
|
||||
* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
|
||||
* muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
|
||||
* has mali_0 and no glitch-free mux.
|
||||
* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
|
||||
* actually manage this glitch-free mux because it does top-to-bottom
|
||||
* updates the each clock tree and switches to the "inactive" one when
|
||||
* CLK_SET_RATE_GATE is set.
|
||||
* Meson8 only has mali_0 and no glitch-free mux.
|
||||
*/
|
||||
static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
|
||||
&meson8b_xtal.hw,
|
||||
&meson8b_mpll2.hw,
|
||||
&meson8b_mpll1.hw,
|
||||
&meson8b_fclk_div7.hw,
|
||||
&meson8b_fclk_div4.hw,
|
||||
&meson8b_fclk_div3.hw,
|
||||
&meson8b_fclk_div5.hw,
|
||||
static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
|
||||
{ .fw_name = "xtal", .name = "xtal", .index = -1, },
|
||||
{ .hw = &meson8b_mpll2.hw, },
|
||||
{ .hw = &meson8b_mpll1.hw, },
|
||||
{ .hw = &meson8b_fclk_div7.hw, },
|
||||
{ .hw = &meson8b_fclk_div4.hw, },
|
||||
{ .hw = &meson8b_fclk_div3.hw, },
|
||||
{ .hw = &meson8b_fclk_div5.hw, },
|
||||
};
|
||||
|
||||
static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
|
||||
@ -1789,8 +1800,8 @@ static struct clk_regmap meson8b_mali_0_sel = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_mali_0_1_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
|
||||
.parent_data = meson8b_mali_0_1_parent_data,
|
||||
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
|
||||
/*
|
||||
* Don't propagate rate changes up because the only changeable
|
||||
* parents are mpll1 and mpll2 but we need those for audio and
|
||||
@ -1830,7 +1841,7 @@ static struct clk_regmap meson8b_mali_0 = {
|
||||
&meson8b_mali_0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1844,8 +1855,8 @@ static struct clk_regmap meson8b_mali_1_sel = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = meson8b_mali_0_1_parent_hws,
|
||||
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
|
||||
.parent_data = meson8b_mali_0_1_parent_data,
|
||||
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
|
||||
/*
|
||||
* Don't propagate rate changes up because the only changeable
|
||||
* parents are mpll1 and mpll2 but we need those for audio and
|
||||
@ -1885,7 +1896,7 @@ static struct clk_regmap meson8b_mali_1 = {
|
||||
&meson8b_mali_1_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1944,8 +1955,10 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp_pll_dco",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_xtal.hw
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.fw_name = "xtal",
|
||||
.name = "xtal",
|
||||
.index = -1,
|
||||
},
|
||||
.num_parents = 1,
|
||||
},
|
||||
@ -3585,7 +3598,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = {
|
||||
|
||||
struct meson8b_nb_data {
|
||||
struct notifier_block nb;
|
||||
struct clk_hw_onecell_data *onecell_data;
|
||||
struct clk_hw *cpu_clk;
|
||||
};
|
||||
|
||||
static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
|
||||
@ -3593,30 +3606,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
|
||||
{
|
||||
struct meson8b_nb_data *nb_data =
|
||||
container_of(nb, struct meson8b_nb_data, nb);
|
||||
struct clk_hw **hws = nb_data->onecell_data->hws;
|
||||
struct clk_hw *cpu_clk_hw, *parent_clk_hw;
|
||||
struct clk *cpu_clk, *parent_clk;
|
||||
struct clk_hw *parent_clk;
|
||||
int ret;
|
||||
|
||||
switch (event) {
|
||||
case PRE_RATE_CHANGE:
|
||||
parent_clk_hw = hws[CLKID_XTAL];
|
||||
/* xtal */
|
||||
parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
|
||||
break;
|
||||
|
||||
case POST_RATE_CHANGE:
|
||||
parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
|
||||
/* cpu_scale_out_sel */
|
||||
parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
|
||||
break;
|
||||
|
||||
default:
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
cpu_clk_hw = hws[CLKID_CPUCLK];
|
||||
cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
|
||||
|
||||
parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
|
||||
|
||||
ret = clk_set_parent(cpu_clk, parent_clk);
|
||||
ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
|
||||
if (ret)
|
||||
return notifier_from_errno(ret);
|
||||
|
||||
@ -3682,20 +3690,26 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
|
||||
meson8b_clk_regmaps[i]->map = map;
|
||||
|
||||
/*
|
||||
* register all clks
|
||||
* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
|
||||
* always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
|
||||
* XTAL clock as input.
|
||||
*/
|
||||
for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
|
||||
if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
|
||||
i = CLKID_PLL_FIXED;
|
||||
else
|
||||
i = CLKID_XTAL;
|
||||
|
||||
/* register all clks */
|
||||
for (; i < CLK_NR_CLKS; i++) {
|
||||
/* array might be sparse */
|
||||
if (!clk_hw_onecell_data->hws[i])
|
||||
continue;
|
||||
|
||||
ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
|
||||
ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
|
||||
if (ret)
|
||||
return;
|
||||
}
|
||||
|
||||
meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
|
||||
meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
|
||||
|
||||
/*
|
||||
* FIXME we shouldn't program the muxes in notifier handlers. The
|
||||
|
||||
4
include/dt-bindings/clock/meson8-ddr-clkc.h
Normal file
4
include/dt-bindings/clock/meson8-ddr-clkc.h
Normal file
@ -0,0 +1,4 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#define DDR_CLKID_DDR_PLL_DCO 0
|
||||
#define DDR_CLKID_DDR_PLL 1
|
||||
@ -627,6 +627,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
* @clk: clock source
|
||||
* @rate: desired clock rate in Hz
|
||||
*
|
||||
* Updating the rate starts at the top-most affected clock and then
|
||||
* walks the tree down to the bottom-most clock that needs updating.
|
||||
*
|
||||
* Returns success (0) or negative errno.
|
||||
*/
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate);
|
||||
|
||||
Reference in New Issue
Block a user