Merge "clk: qcom: gpucc: Add support for reset for parrot"
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@ -639,6 +639,7 @@ static const struct qcom_reset_map gpu_cc_parrot_resets[] = {
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[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
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[GPUCC_GPU_CC_RBCPR_BCR] = { 0x91e0 },
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[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
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[GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR] = { 0x9538, 0 },
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};
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static const struct regmap_config gpu_cc_parrot_regmap_config = {
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@ -677,6 +678,8 @@ static int gpu_cc_parrot_probe(struct platform_device *pdev)
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clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
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clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
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regmap_write(regmap, 0x9534, 0x0);
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ret = qcom_cc_really_probe(pdev, &gpu_cc_parrot_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_PARROT_H
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@ -46,5 +46,6 @@
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#define GPUCC_GPU_CC_GX_BCR 7
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#define GPUCC_GPU_CC_RBCPR_BCR 8
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#define GPUCC_GPU_CC_XO_BCR 9
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#define GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 10
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#endif
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