518 lines
14 KiB
C
518 lines
14 KiB
C
/*
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* TC956X ethernet driver.
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*
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* dwxgmac2_descs.c
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*
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* Copyright (C) 2018 Synopsys, Inc. and/or its affiliates.
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* Copyright (C) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* This file has been derived from the STMicro and Synopsys Linux driver,
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* and developed or modified for TC956X.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/*! History:
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* 20 Jan 2021 : Initial Version
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* VERSION : 00-01
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*
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* 15 Mar 2021 : Base lined
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* VERSION : 01-00
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* 15 Jul 2021 : 1. USXGMII/XFI/SGMII/RGMII interface supported without module parameter
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* VERSION : 01-00-02
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* 20 Jul 2021 : 1. Debug prints removed
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* VERSION : 01-00-03
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*/
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#include "tc956xmac_inc.h"
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#include "tc956xmac.h"
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#include "common.h"
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#include "dwxgmac2.h"
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static int dwxgmac2_get_tx_status(struct tc956xmac_priv *priv, void *data,
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struct tc956xmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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int ret = tx_done;
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if (unlikely(tdes3 & XGMAC_TDES3_OWN))
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return tx_dma_own;
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if (likely(!(tdes3 & XGMAC_TDES3_LD)))
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return tx_not_ls;
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return ret;
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}
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static int dwxgmac2_get_rx_status(struct tc956xmac_priv *priv, void *data,
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struct tc956xmac_extra_stats *x,
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struct dma_desc *p)
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{
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unsigned int rdes3 = le32_to_cpu(p->des3);
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if (unlikely(rdes3 & XGMAC_RDES3_OWN))
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return dma_own;
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if (unlikely(rdes3 & XGMAC_RDES3_CTXT))
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return discard_frame;
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if (likely(!(rdes3 & XGMAC_RDES3_LD)))
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return rx_not_ls;
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if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD)))
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return discard_frame;
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return good_frame;
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}
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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static int dwxgmac2_get_tx_len(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
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}
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static int dwxgmac2_get_tx_owner(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
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}
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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static void dwxgmac2_set_tx_owner(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
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}
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static void dwxgmac2_set_rx_owner(struct tc956xmac_priv *priv,
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struct dma_desc *p, int disable_rx_ic)
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{
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p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN);
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if (!disable_rx_ic)
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p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
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}
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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static int dwxgmac2_get_tx_ls(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
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}
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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static int dwxgmac2_get_rx_frame_len(struct tc956xmac_priv *priv,
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struct dma_desc *p, int rx_coe)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL);
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}
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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static void dwxgmac2_enable_tx_timestamp(struct tc956xmac_priv *priv,
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struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE);
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}
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static int dwxgmac2_get_tx_timestamp_status(struct tc956xmac_priv *priv,
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struct dma_desc *p)
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{
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return 0; /* Not supported */
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}
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static inline void dwxgmac2_get_timestamp(struct tc956xmac_priv *priv,
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void *desc, u32 ats, u64 *ts)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns = 0;
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ns += le32_to_cpu(p->des1) * 1000000000ULL;
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ns += le32_to_cpu(p->des0);
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*ts = ns;
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netdev_dbg(priv->dev, "%s: timestamp in ns = 0x%llx", __func__, ns);
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}
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static int dwxgmac2_rx_check_timestamp(struct tc956xmac_priv *priv, void *desc)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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bool desc_valid, ts_valid;
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dma_rmb();
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desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
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ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
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if (likely(desc_valid && ts_valid)) {
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if ((le32_to_cpu(p->des0) == 0xffffffff) && (le32_to_cpu(p->des1) == 0xffffffff))
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return -EINVAL;
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netdev_dbg(priv->dev, "%s: Rx timestamp Low = 0x%x", __func__,
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le32_to_cpu(p->des0));
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netdev_dbg(priv->dev, "%s: Rx timestamp High = 0x%x", __func__,
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le32_to_cpu(p->des1));
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return 0;
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}
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return -EINVAL;
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}
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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static int dwxgmac2_get_rx_timestamp_status(struct tc956xmac_priv *priv,
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void *desc, void *next_desc,
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u32 ats)
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{
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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int ret = -EBUSY;
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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if (likely(rdes3 & XGMAC_RDES3_CDA))
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ret = dwxgmac2_rx_check_timestamp(priv, next_desc);
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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return !ret;
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}
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static void dwxgmac2_init_rx_desc(struct tc956xmac_priv *priv,
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struct dma_desc *p, int disable_rx_ic,
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int mode, int end, int bfsize)
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{
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dwxgmac2_set_rx_owner(priv, p, disable_rx_ic);
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}
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static void dwxgmac2_init_tx_desc(struct tc956xmac_priv *priv,
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struct dma_desc *p, int mode, int end)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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/**
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* dwxgmac2_prepare_tx_desc - Fill descriptors based on the provided input
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* parameters.
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*
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* @p: pointer to dma_desc descriptor
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* @is_fs: 1 - first descriptor, 0 - not first descriptor
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* @len: buffer length
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* @csum_flag: checksum flag 1 - Enable HW checksum computaion, 0 - disable
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* @crc_pad: CRC padding configuration
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* @mode: descriptor mode
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* @tx_own: descriptor own bit setting
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* @ls: 1 - last descriptor, 0 - not last descriptor
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* @tot_pkt_len: total packet length
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*/
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static void dwxgmac2_prepare_tx_desc(struct tc956xmac_priv *priv,
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struct dma_desc *p, int is_fs, int len,
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bool csum_flag, u32 crc_pad, int mode,
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bool tx_own, bool ls,
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unsigned int tot_pkt_len)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
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tdes3 |= tot_pkt_len & XGMAC_TDES3_FL;
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if (is_fs)
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tdes3 |= XGMAC_TDES3_FD;
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else
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tdes3 &= ~XGMAC_TDES3_FD;
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if (csum_flag)
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tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
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else
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tdes3 &= ~XGMAC_TDES3_CIC;
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if (crc_pad)
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tdes3 |= crc_pad << XGMAC_TDES3_CPC_SHIFT;
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else
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tdes3 &= ~XGMAC_TDES3_CPC;
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_prepare_tso_tx_desc(struct tc956xmac_priv *priv,
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struct dma_desc *p, int is_fs,
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int len1, int len2, bool tx_own,
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bool ls, unsigned int tcphdrlen,
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unsigned int tcppayloadlen)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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if (len1)
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p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
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if (len2)
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p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
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XGMAC_TDES2_B2L);
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if (is_fs) {
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tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
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tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
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XGMAC_TDES3_THL;
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tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
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} else {
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tdes3 &= ~XGMAC_TDES3_FD;
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}
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_release_tx_desc(struct tc956xmac_priv *priv,
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struct dma_desc *p, int mode)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwxgmac2_set_tx_ic(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC);
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}
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static void dwxgmac2_set_mss(struct tc956xmac_priv *priv,
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struct dma_desc *p, unsigned int mss)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = cpu_to_le32(mss);
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p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
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}
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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static void dwxgmac2_get_addr(struct tc956xmac_priv *priv,
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struct dma_desc *p, unsigned int *addr)
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{
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*addr = le32_to_cpu(p->des0);
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}
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#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
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static void dwxgmac2_set_addr(struct tc956xmac_priv *priv,
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struct dma_desc *p, dma_addr_t addr)
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{
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//printk("%s, buff addr = 0x%llx\n",__func__, addr);
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p->des0 = cpu_to_le32(lower_32_bits(addr));
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#ifdef TC956X
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/* Set the mask for physical address access */
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p->des1 = cpu_to_le32(TC956X_HOST_PHYSICAL_ADRS_MASK |
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(upper_32_bits(addr) & 0xF));
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#else
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p->des1 = cpu_to_le32(upper_32_bits(addr));
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#endif
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//printk(" pdes0 = 0x%x. pdes1 = 0x%x\n", p->des0, p->des1);
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}
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static void dwxgmac2_clear(struct tc956xmac_priv *priv, struct dma_desc *p)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static int dwxgmac2_get_rx_hash(struct tc956xmac_priv *priv,
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struct dma_desc *p, u32 *hash,
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enum pkt_hash_types *type)
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{
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unsigned int rdes3 = le32_to_cpu(p->des3);
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u32 ptype;
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if (rdes3 & XGMAC_RDES3_RSV) {
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ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
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switch (ptype) {
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case XGMAC_L34T_IP4TCP:
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case XGMAC_L34T_IP4UDP:
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case XGMAC_L34T_IP6TCP:
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case XGMAC_L34T_IP6UDP:
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*type = PKT_HASH_TYPE_L4;
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break;
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default:
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*type = PKT_HASH_TYPE_L3;
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break;
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}
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*hash = le32_to_cpu(p->des1);
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return 0;
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}
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return -EINVAL;
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}
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static int dwxgmac2_get_rx_header_len(struct tc956xmac_priv *priv,
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struct dma_desc *p, unsigned int *len)
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{
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if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
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*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
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return 0;
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}
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static void dwxgmac2_set_sec_addr(struct tc956xmac_priv *priv,
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struct dma_desc *p, dma_addr_t addr)
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{
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p->des2 = cpu_to_le32(lower_32_bits(addr));
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p->des3 = cpu_to_le32(upper_32_bits(addr));
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}
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static void dwxgmac2_set_sarc(struct tc956xmac_priv *priv,
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struct dma_desc *p, u32 sarc_type)
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{
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sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
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p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
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}
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static void dwxgmac2_set_vlan_tag(struct tc956xmac_priv *priv,
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struct dma_desc *p, u16 tag, u16 inner_tag,
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u32 inner_type)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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/* Inner VLAN */
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if (inner_type) {
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u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
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des &= XGMAC_TDES2_IVT;
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p->des2 = cpu_to_le32(des);
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des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
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des &= XGMAC_TDES3_IVTIR;
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p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
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}
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/* Outer VLAN */
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p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT);
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p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV);
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p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
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}
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static void dwxgmac2_set_vlan(struct tc956xmac_priv *priv, struct dma_desc *p,
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u32 type)
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{
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type <<= XGMAC_TDES2_VTIR_SHIFT;
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p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
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}
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#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
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static void dwxgmac2_set_tbs(struct tc956xmac_priv *priv, struct dma_edesc *p,
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u32 sec, u32 nsec, bool lt_valid)
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{
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p->des4 = 0;
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if (lt_valid)
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p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
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p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
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p->des6 = 0;
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p->des7 = 0;
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}
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static void dwxgmac2_set_ostc(struct tc956xmac_priv *priv,
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struct dma_desc *p, u32 ttsh, u32 ttsl)
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{
|
|
p->des2 = 0;
|
|
|
|
/* Set the timestamp for the DMA to use for doing one-step correction */
|
|
p->des0 = cpu_to_le32(ttsl);
|
|
p->des1 = cpu_to_le32(ttsh);
|
|
|
|
/* One-Step Timestamp Correction Enable */
|
|
p->des3 |= cpu_to_le32(XGMAC_TDES3_OSTC | XGMAC_TDES3_TCMSSV);
|
|
|
|
/* Set Context Type for Context descriptor */
|
|
p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
|
|
}
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
|
|
const struct tc956xmac_desc_ops dwxgmac210_desc_ops = {
|
|
.tx_status = dwxgmac2_get_tx_status,
|
|
.rx_status = dwxgmac2_get_rx_status,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.get_tx_len = dwxgmac2_get_tx_len,
|
|
.get_tx_owner = dwxgmac2_get_tx_owner,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
.set_tx_owner = dwxgmac2_set_tx_owner,
|
|
.set_rx_owner = dwxgmac2_set_rx_owner,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.get_tx_ls = dwxgmac2_get_tx_ls,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
.get_rx_frame_len = dwxgmac2_get_rx_frame_len,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,
|
|
.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.get_timestamp = dwxgmac2_get_timestamp,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
.set_tx_ic = dwxgmac2_set_tx_ic,
|
|
.prepare_tx_desc = dwxgmac2_prepare_tx_desc,
|
|
.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,
|
|
.release_tx_desc = dwxgmac2_release_tx_desc,
|
|
.init_rx_desc = dwxgmac2_init_rx_desc,
|
|
.init_tx_desc = dwxgmac2_init_tx_desc,
|
|
.set_mss = dwxgmac2_set_mss,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.get_addr = dwxgmac2_get_addr,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
.set_addr = dwxgmac2_set_addr,
|
|
.clear = dwxgmac2_clear,
|
|
.get_rx_hash = dwxgmac2_get_rx_hash,
|
|
.get_rx_header_len = dwxgmac2_get_rx_header_len,
|
|
.set_sec_addr = dwxgmac2_set_sec_addr,
|
|
.set_sarc = dwxgmac2_set_sarc,
|
|
.set_vlan_tag = dwxgmac2_set_vlan_tag,
|
|
.set_vlan = dwxgmac2_set_vlan,
|
|
#ifdef TC956X_UNSUPPORTED_UNTESTED_FEATURE
|
|
.set_tbs = dwxgmac2_set_tbs,
|
|
.set_ostc = dwxgmac2_set_ostc,
|
|
#endif /* TC956X_UNSUPPORTED_UNTESTED_FEATURE */
|
|
};
|