Common framework changes were added to capture KPI's,
this will help in capturing KPI numbers for all
interfaces spi, i2c, i3c and uart.
This implementation will help in capturing Tx, Rx
data path kpi's and geni resource enablement
KPI data as well.
To enable the uart kpi capture user should use the
below sysfs flag, by default capture_kpi sysfs flag
is disabled.
Ex: To enable:
echo 1 > /sys/bus/platform/devices/898000.qcom,qup_uart/capture_kpi
To disable:
echo 0 > /sys/bus/platform/devices/898000.qcom,qup_uart/capture_kpi
A new IPC log file is created to log the function
entry/exit timestamps which will help to capture the kpi's.
Ex:
cat /sys/kernel/debug/ipc_logging/898000.qcom,qup_uart_kpi/log.
Change-Id: I2e69fd2c7e505691904b5913bc425461f73d6fd1
Signed-off-by: Srikanth Nanavalla <quic_snanaval@quicinc.com>
Directly including linux/rwlock.h breaks RT build failure.
Fix this by including linux/spinlock.h which includes the
correct rwlock header based on the selected PREEMPT configuration.
Change-Id: I42d3f7ec9a136f41626ca2678da00d325b896289
Signed-off-by: Kassey Li <quic_yingangl@quicinc.com>
If userspace changes the governor to a different one than waltgov,
ensure that capacities are unnecessarily capped and accurately reflect
the current frequency's true capacity.
Change-Id: I04c392721a96ff3d03e9438dd3a97777f0d9fd2b
Signed-off-by: Shaleen Agrawal <quic_shalagra@quicinc.com>
Create a waltgov_disabled flag to indicate if the WALT governor is the
active governor.
This will be used by the followup patch to determine when to modify
capacities.
Change-Id: Ic1509efbd123fd471536e75d54efcf6880a81627
Signed-off-by: Shaleen Agrawal <quic_shalagra@quicinc.com>
Implement a paravirtualized smmu v3 driver which registers to
the IOMMU framework. This driver manages stage-1 translations for
clients using smmu v3. It passes information of context
descriptors, stage-1 page table address and other parameters
via scm calls to a backend SMMU-v3 driver which runs at a
higher exception level, this backend driver is supposed to
internally program the smmu v3 registers.
Add snapshot for ARM-SMMUV3 paravirtualized driver from
msm-5.15 branch.
commit 78a4b713 ("iommu/arm-smmu-v3: Add a paravirtualized
ARM-SMMU V3 driver").
Change-Id: I3fd2d501c65cf0daecc691432963f422047b375a
Signed-off-by: Singa Reddy Dasari <quic_singredd@quicinc.com>
Current code assumes that logical CPU number & physical
CPU has 1:1 mapping and accordingly get core-hang
registers from DT which are placed linearly with
increasing order of logical CPU numbers.
But if any CPU is not available then we will end up
using wrong registers because 1:1 mapping is broken
as we are having logically contiguous CPU numbers even
if physical cpus are not available.
To resolve this we are using new property "qcom,chd-percpu-info"
from DT which has core-hang registers wrt CPU phandles.
This driver is taking those registers based on CPU node
availability and mapping the registers to corresponding
logical CPU index.
Change-Id: Icf9b427a2760c0a0e742aecda7a07412085061a6
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Read registers values from DT till nr_cpu_ids.
Change-Id: I9f6432bbd279790b76d8bb7b68db7f46e8c9c05e
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Add support to check the available cpus for each cluster.
Change-Id: I68e7fde67365a1d85d6533b45ffae75c0f23e3d1
Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com>
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Add a new sysfs node 'irq_affinity_support' which is helpful
for enable and disable "Dynamic IRQ Affinity" feature.
Change-Id: I732777d9397dc8485d496600bd48785cf23151c4
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Add support for Cliffs7 variant of Cliffs in socinfo.
Change-Id: I8b9d12f05edd28d229f1bd465310070cec549796
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
If device tree includes 'qcom,prime-mask' node, enable
dynamic irq affinity feature, else keep it disable by
default. As REQ_HIPRI has been replaced with REQ_POLLED,
hence using this flag in ufs_qcom_hook_compl_command will
complete the request in hard irq context.
With this, a significant improvement is observed with
UFS 2.x devices.
--------------------------------------------------------------
UFS 2.2 Hynix |
-------------------------------------------------------------
operation | default | with irq affinity feature |
-------------------------------------------------------------
Rnd Read (IOPS) | 29713 | 43221 |
Rnd Write (IOPS) | 28094 | 44087 |
-------------------------------------------------------------..
Change-Id: I63b0e5b2bc38a08c42a2332e8fc691a94e4983f6
Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
In MCQ mode, if AHIT is about to expire, updating SQ tail pointer cannot
stop AHIT from expiring. When this corner case happens, Data command and
Hibernate command goes to Unipro together. And because Unipro gives
priority to Hibernate command, hence Data command is ignored, leading to
Data command timeout (task abort). To work around this corner case, the
essense is to stop AHIT timer from expiring before updating the SQ tail
pointer. The simplest way to stop AHIT timer from expiring is just
re-programming AHIT as 0. AHIT will be enabled back once there is no
active commands in UFS host controller.
Change-Id: I3e04468ac1321ccccbef86d9ed484e0aa91e3fd6
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
Currently, the consolidate build uses COMMON_GKI_MODULES as the
implicit build output list. Instead, use the new get_gki_modules_list
macro to get the arch-specific list.
Change-Id: Ia97ed23fc9ac79999681f1357ff86c36e655ac18
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
Update the frequency table of GCC clocks as per the latest
SW plan. While at it, update enable_reg, hwcg_reg for few
videocc shift clocks on cliffs platform.
Change-Id: Ie5d4de14b0b4bbdd39f74eac845744a00e0b4df2
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
