walt code currently uses rcu_dereference to access rd->pd. As we are
not dereferencing the pointer use rcu_access_pointer instead of
rcu_dereference.
Change-Id: I5ef0d12de4ae89ce423b421d1d2de28fc7759c00
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
rproc->priv is incorrectly being dereferenced and assigned
without checking if rproc can be NULL however, the check
for this exist in the code, so fix this issue by doing
the handling appropriately.
(cherry picked from commit 2b05138c888f180a00c766f57dedb98a8863da0a).
Change-Id: I990a52ffc2a713c0e814fabfce4931e9bc1c3ac9
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Compliance TypeC certification--TD 4.7.4 throws error saying "The put
does not cease USB communication" because currently the stop host
procedure set the role back to device and flushes the drd-work first
then disconnects phys. However the Analyzer by this time will consider
that the PHY is still active and therefore throw such error assuming
the test failed.
Fix this by moving the PHY disconnect notifiers before the role_switch
and flush work. Additionally disconnect ssphy first then the hsphy so
that the LFPS packets and be turned off as quickly as possible.
Change-Id: I6ea4665360dc8b92992672428d0563b8c1ea19e9
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
Enable config for governor and qcom stat driver. Also, added
required modules for enabled configs in anorak.bzl file.
Change-Id: I40eaead56ded3abf6c6ab43567bdbcc50e6f760a
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Add snapshot of drv name on ANORAK from msm-5.10 branch to
get stats information
commit 4545acd1dc3c ("soc: qcom: sys_pm_vx: Add drv_names
for anorak").
Change-Id: I3ca54e4091a5d3555f3f77517cbf5752c7d7b1d2
Signed-off-by: Tushar Nimkar <quic_tnimkar@quicinc.com>
Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
In PHY calibration table for Gear 4, entries for registers
QSERDES_TX0_LANE_MODE_3 and QSERDES_TX1_LANE_MODE_3 are missing.
Hence, setting the right configuration for the above mentioned
registers.
Change-Id: Ia5c5560d14b2ecbf5b9ae32a423774394e71d527
Signed-off-by: Anjana Hari <quic_ahari@quicinc.com>
Fix the condition check that overrides the number of
smr/context banks in the system.
Change-Id: I242375ab711f3688a7c8a24e598d1e4a2a7fac17
Signed-off-by: Charan Teja Reddy <quic_charante@quicinc.com>
Signed-off-by: Shreyas K K <quic_shrekk@quicinc.com>
We should close nonatomic handle which is already opened.
Change-Id: Id789f74e0cfbfa918bc7450a559fc0fdf51b65d2
Signed-off-by: Yuhang Ji <quic_yuhaji@quicinc.com>
Enable watchdog support for anorak.
Change-Id: I81b195570c692187c7ed27f262162c9b728fdd6f
Signed-off-by: amatariy <quic_amatariy@quicinc.com>
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
When byte-cntr irq count doesn't match up with the data size in
ETR sink, there will be delay issue to send the data to host.
Count the irq number in small size transfer function when such
case happens.
Change-Id: I60428e1d9916fd0dde8c87f3f81c8b887b7e448b
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
It fix the restore failure in hibernation.
Change-Id: I2b0fdcbb9f213e27941a56479157a52e6f822dd7
Signed-off-by: Raghava Chowdam <quic_rchowdam@quicinc.com>
Normally, hypervisor virtualizes IDR registers to inform HLOS of the
number of context banks and smr registers available. However, in certain
debug modes, this support is not available. Add an alternate method for
HLOS to gather this information.
Change-Id: I73194daa06ca2a499f75f9b9173f9afc2f691f49
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Shreyas K K <quic_shrekk@quicinc.com>
Populate the best_parent_rate property of parent_req structure with
rate of apcs_cpu_pll parent, as parent_req gets passed down the
__clk_determine_rate function and does not have the best_parent_rate
property populated at any point for apcs_cpu_pll. It causes the
parent_rate to be passed as 0 to pll round_rate APIs which causes
kernel crash when doing rate calculation.
Also, Correct vco config value from 1 to 0.
Change-Id: Iaa6a7d9bc039ac883a555f2f52e9882573fa943d
Signed-off-by: Prerna Singh <quic_prersing@quicinc.com>
The hw->init is no longer valid after the HW clock is registered with
the clock framework, thus clean up the clock enable/disable.
Also, update if statement to check whether the clk is disabled & then
only enable the clk.
Change-Id: I965cd1d5c14efd2bea8cc220f2b19ed1f3ddfb8c
Signed-off-by: Prerna Singh <quic_prersing@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
The address offsets of AODBG csr is different from current CSR offsets.
Add the timestamp control registers and heartbeat regsiters config for
AODBG CSR.
Change-Id: I4f26a0092d60f1a55c8680fb80a6dd2abbc3c809
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Sometimes APSS PCIe driver fails to send command to ADSP PCIe driver
using RPMSG at the time of bootup where ADSP RPMSG interface is busy
handling many RPMSG request from different clients from APSS.
Increase the retries of sending command over RPMSG from APPS to ADSP
from 5 to 20 which eventually increases the timeout value from 25ms
to 100ms.
Change-Id: Id87375d0a669ef3b8c511847c84564a1f5456b19
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
