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ANDROID: virt: geniezone: Refactoring vcpu to align with upstream v6

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The used definitions related to GZVM_REG_* are below and move them to
uapi header file `gzvm.h`.
- Keep `GZVM_REG_SIZE_SHIFT` and `GZVM_REG_SIZE_MASK` so that we can
  determine the reg size.
- The other definitions related to GZVM_REG_* are used by crosvm.
- Rename the definitions to make it easy to understand.

Also removed the unused definitions related to GZVM_REG_* in
gzvm_arch.h and fixed sparse warnings.

Change-Id: I7f709f2532b95d418d22beeb4a46257afa4d92f2
Signed-off-by: kevenny hsieh <kevenny.hsieh@mediatek.com>
Signed-off-by: Yingshiuan Pan <yingshiuan.pan@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Signed-off-by: Yi-De Wu <yi-de.wu@mediatek.com>
Bug: 301179926
Link: https://lore.kernel.org/all/20230919111210.19615-8-yi-de.wu@mediatek.com/
This commit is contained in:
Yi-De Wu 2023-08-21 19:04:34 +08:00 committed by Todd Kjos
parent e348fe6d2d
commit f9291d7af0
4 changed files with 38 additions and 47 deletions
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8
arch/arm64/geniezone/vcpu.c
View File

@ -18,14 +18,6 @@ int gzvm_arch_vcpu_update_one_reg(struct gzvm_vcpu *vcpu, __u64 reg_id,
unsigned long a1;
int ret;
/* reg id follows KVM's encoding */
switch (reg_id & GZVM_REG_ARM_COPROC_MASK) {
case GZVM_REG_ARM_CORE:
break;
default:
return -EOPNOTSUPP;
}
a1 = assemble_vm_vcpu_tuple(vcpu->gzvm->vm_id, vcpu->vcpuid);
if (!is_write) {
ret = gzvm_hypcall_wrapper(MT_HVC_GZVM_GET_ONE_REG,

30
arch/arm64/include/uapi/asm/gzvm_arch.h
View File

@ -8,36 +8,6 @@
#include <linux/types.h>
/*
* Architecture specific registers are to be defined in arch headers and
* ORed with the arch identifier.
*/
#define GZVM_REG_ARM 0x4000000000000000ULL
#define GZVM_REG_ARM64 0x6000000000000000ULL
#define GZVM_REG_SIZE_SHIFT 52
#define GZVM_REG_SIZE_MASK 0x00f0000000000000ULL
#define GZVM_REG_SIZE_U8 0x0000000000000000ULL
#define GZVM_REG_SIZE_U16 0x0010000000000000ULL
#define GZVM_REG_SIZE_U32 0x0020000000000000ULL
#define GZVM_REG_SIZE_U64 0x0030000000000000ULL
#define GZVM_REG_SIZE_U128 0x0040000000000000ULL
#define GZVM_REG_SIZE_U256 0x0050000000000000ULL
#define GZVM_REG_SIZE_U512 0x0060000000000000ULL
#define GZVM_REG_SIZE_U1024 0x0070000000000000ULL
#define GZVM_REG_SIZE_U2048 0x0080000000000000ULL
#define GZVM_REG_ARCH_MASK 0xff00000000000000ULL
/* If you need to interpret the index values, here is the key: */
#define GZVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
#define GZVM_REG_ARM_COPROC_SHIFT 16
/* Normal registers are mapped as coprocessor 16. */
#define GZVM_REG_ARM_CORE (0x0010 << GZVM_REG_ARM_COPROC_SHIFT)
#define GZVM_REG_ARM_CORE_REG(name) \
(offsetof(struct gzvm_regs, name) / sizeof(__u32))
#define GZVM_VGIC_NR_SGIS 16
#define GZVM_VGIC_NR_PPIS 16
#define GZVM_VGIC_NR_PRIVATE_IRQS (GZVM_VGIC_NR_SGIS + GZVM_VGIC_NR_PPIS)

19
drivers/virt/geniezone/gzvm_vcpu.c
View File

@ -16,7 +16,7 @@
#define ITOA_MAX_LEN 12
static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
void * __user argp,
void __user *argp,
bool is_write)
{
struct gzvm_one_reg reg;
@ -32,9 +32,15 @@ static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
reg_size = (reg.id & GZVM_REG_SIZE_MASK) >> GZVM_REG_SIZE_SHIFT;
reg_size = BIT(reg_size);
if (reg_size != 1 && reg_size != 2 && reg_size != 4 && reg_size != 8)
return -EINVAL;
if (is_write) {
/* GZ hypervisor would filter out invalid vcpu register access */
if (copy_from_user(&data, reg_addr, reg_size))
return -EFAULT;
} else {
return -EOPNOTSUPP;
}
ret = gzvm_arch_vcpu_update_one_reg(vcpu, reg.id, is_write, &data);
@ -42,11 +48,6 @@ static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
if (ret)
return ret;
if (!is_write) {
if (copy_to_user(reg_addr, &data, reg_size))
return -EFAULT;
}
return 0;
}
@ -84,7 +85,7 @@ static bool gzvm_vcpu_handle_mmio(struct gzvm_vcpu *vcpu)
* * 0 - Success.
* * Negative - Failure.
*/
static long gzvm_vcpu_run(struct gzvm_vcpu *vcpu, void * __user argp)
static long gzvm_vcpu_run(struct gzvm_vcpu *vcpu, void __user *argp)
{
bool need_userspace = false;
u64 exit_reason = 0;
@ -163,8 +164,8 @@ static long gzvm_vcpu_ioctl(struct file *filp, unsigned int ioctl,
ret = gzvm_vcpu_run(vcpu, argp);
break;
case GZVM_GET_ONE_REG:
/* is_write */
ret = gzvm_vcpu_update_one_reg(vcpu, argp, false);
/* !is_write */
ret = -EOPNOTSUPP;
break;
case GZVM_SET_ONE_REG:
/* is_write */

28
include/uapi/linux/gzvm.h
View File

@ -27,6 +27,34 @@
/* GZVM_CAP_PVM_SET_PROTECTED_VM only sets protected but not load pvmfw */
#define GZVM_CAP_PVM_SET_PROTECTED_VM 2
/*
* Architecture specific registers are to be defined and ORed with
* the arch identifier.
*/
#define GZVM_REG_ARCH_ARM64 0x6000000000000000ULL
#define GZVM_REG_ARCH_MASK 0xff00000000000000ULL
/*
* Reg size = BIT((reg.id & GZVM_REG_SIZE_MASK) >> GZVM_REG_SIZE_SHIFT) bytes
*/
#define GZVM_REG_SIZE_SHIFT 52
#define GZVM_REG_SIZE_MASK 0x00f0000000000000ULL
#define GZVM_REG_SIZE_U8 0x0000000000000000ULL
#define GZVM_REG_SIZE_U16 0x0010000000000000ULL
#define GZVM_REG_SIZE_U32 0x0020000000000000ULL
#define GZVM_REG_SIZE_U64 0x0030000000000000ULL
#define GZVM_REG_SIZE_U128 0x0040000000000000ULL
#define GZVM_REG_SIZE_U256 0x0050000000000000ULL
#define GZVM_REG_SIZE_U512 0x0060000000000000ULL
#define GZVM_REG_SIZE_U1024 0x0070000000000000ULL
#define GZVM_REG_SIZE_U2048 0x0080000000000000ULL
/* Register type definitions */
#define GZVM_REG_TYPE_SHIFT 16
/* Register type: general purpose */
#define GZVM_REG_TYPE_GENERAL (0x10 << GZVM_REG_TYPE_SHIFT)
/* GZVM ioctls */
#define GZVM_IOC_MAGIC 0x92 /* gz */