diff --git a/arch/arm64/geniezone/vcpu.c b/arch/arm64/geniezone/vcpu.c
index 95681fd66656..f6670bd77ad6 100644
--- a/arch/arm64/geniezone/vcpu.c
+++ b/arch/arm64/geniezone/vcpu.c
@@ -18,14 +18,6 @@ int gzvm_arch_vcpu_update_one_reg(struct gzvm_vcpu *vcpu, __u64 reg_id,
 	unsigned long a1;
 	int ret;
 
-	/* reg id follows KVM's encoding */
-	switch (reg_id & GZVM_REG_ARM_COPROC_MASK) {
-	case GZVM_REG_ARM_CORE:
-		break;
-	default:
-		return -EOPNOTSUPP;
-	}
-
 	a1 = assemble_vm_vcpu_tuple(vcpu->gzvm->vm_id, vcpu->vcpuid);
 	if (!is_write) {
 		ret = gzvm_hypcall_wrapper(MT_HVC_GZVM_GET_ONE_REG,
diff --git a/arch/arm64/include/uapi/asm/gzvm_arch.h b/arch/arm64/include/uapi/asm/gzvm_arch.h
index ceec2f2677e2..4e80a060f385 100644
--- a/arch/arm64/include/uapi/asm/gzvm_arch.h
+++ b/arch/arm64/include/uapi/asm/gzvm_arch.h
@@ -8,36 +8,6 @@
 
 #include <linux/types.h>
 
-/*
- * Architecture specific registers are to be defined in arch headers and
- * ORed with the arch identifier.
- */
-#define GZVM_REG_ARM		0x4000000000000000ULL
-#define GZVM_REG_ARM64		0x6000000000000000ULL
-
-#define GZVM_REG_SIZE_SHIFT	52
-#define GZVM_REG_SIZE_MASK	0x00f0000000000000ULL
-#define GZVM_REG_SIZE_U8	0x0000000000000000ULL
-#define GZVM_REG_SIZE_U16	0x0010000000000000ULL
-#define GZVM_REG_SIZE_U32	0x0020000000000000ULL
-#define GZVM_REG_SIZE_U64	0x0030000000000000ULL
-#define GZVM_REG_SIZE_U128	0x0040000000000000ULL
-#define GZVM_REG_SIZE_U256	0x0050000000000000ULL
-#define GZVM_REG_SIZE_U512	0x0060000000000000ULL
-#define GZVM_REG_SIZE_U1024	0x0070000000000000ULL
-#define GZVM_REG_SIZE_U2048	0x0080000000000000ULL
-
-#define GZVM_REG_ARCH_MASK	0xff00000000000000ULL
-
-/* If you need to interpret the index values, here is the key: */
-#define GZVM_REG_ARM_COPROC_MASK	0x000000000FFF0000
-#define GZVM_REG_ARM_COPROC_SHIFT	16
-
-/* Normal registers are mapped as coprocessor 16. */
-#define GZVM_REG_ARM_CORE		(0x0010 << GZVM_REG_ARM_COPROC_SHIFT)
-#define GZVM_REG_ARM_CORE_REG(name)	\
-	(offsetof(struct gzvm_regs, name) / sizeof(__u32))
-
 #define GZVM_VGIC_NR_SGIS		16
 #define GZVM_VGIC_NR_PPIS		16
 #define GZVM_VGIC_NR_PRIVATE_IRQS	(GZVM_VGIC_NR_SGIS + GZVM_VGIC_NR_PPIS)
diff --git a/drivers/virt/geniezone/gzvm_vcpu.c b/drivers/virt/geniezone/gzvm_vcpu.c
index 72bd122a8be7..77138e749e9a 100644
--- a/drivers/virt/geniezone/gzvm_vcpu.c
+++ b/drivers/virt/geniezone/gzvm_vcpu.c
@@ -16,7 +16,7 @@
 #define ITOA_MAX_LEN 12
 
 static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
-				     void * __user argp,
+				     void __user *argp,
 				     bool is_write)
 {
 	struct gzvm_one_reg reg;
@@ -32,9 +32,15 @@ static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
 	reg_size = (reg.id & GZVM_REG_SIZE_MASK) >> GZVM_REG_SIZE_SHIFT;
 	reg_size = BIT(reg_size);
 
+	if (reg_size != 1 && reg_size != 2 && reg_size != 4 && reg_size != 8)
+		return -EINVAL;
+
 	if (is_write) {
+		/* GZ hypervisor would filter out invalid vcpu register access */
 		if (copy_from_user(&data, reg_addr, reg_size))
 			return -EFAULT;
+	} else {
+		return -EOPNOTSUPP;
 	}
 
 	ret = gzvm_arch_vcpu_update_one_reg(vcpu, reg.id, is_write, &data);
@@ -42,11 +48,6 @@ static long gzvm_vcpu_update_one_reg(struct gzvm_vcpu *vcpu,
 	if (ret)
 		return ret;
 
-	if (!is_write) {
-		if (copy_to_user(reg_addr, &data, reg_size))
-			return -EFAULT;
-	}
-
 	return 0;
 }
 
@@ -84,7 +85,7 @@ static bool gzvm_vcpu_handle_mmio(struct gzvm_vcpu *vcpu)
  * * 0			- Success.
  * * Negative		- Failure.
  */
-static long gzvm_vcpu_run(struct gzvm_vcpu *vcpu, void * __user argp)
+static long gzvm_vcpu_run(struct gzvm_vcpu *vcpu, void __user *argp)
 {
 	bool need_userspace = false;
 	u64 exit_reason = 0;
@@ -163,8 +164,8 @@ static long gzvm_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 		ret = gzvm_vcpu_run(vcpu, argp);
 		break;
 	case GZVM_GET_ONE_REG:
-		/* is_write */
-		ret = gzvm_vcpu_update_one_reg(vcpu, argp, false);
+		/* !is_write */
+		ret = -EOPNOTSUPP;
 		break;
 	case GZVM_SET_ONE_REG:
 		/* is_write */
diff --git a/include/uapi/linux/gzvm.h b/include/uapi/linux/gzvm.h
index 14bdd8ec50a3..a432cb7f4ac1 100644
--- a/include/uapi/linux/gzvm.h
+++ b/include/uapi/linux/gzvm.h
@@ -27,6 +27,34 @@
 /* GZVM_CAP_PVM_SET_PROTECTED_VM only sets protected but not load pvmfw */
 #define GZVM_CAP_PVM_SET_PROTECTED_VM		2
 
+/*
+ * Architecture specific registers are to be defined and ORed with
+ * the arch identifier.
+ */
+#define GZVM_REG_ARCH_ARM64	0x6000000000000000ULL
+#define GZVM_REG_ARCH_MASK	0xff00000000000000ULL
+
+/*
+ * Reg size = BIT((reg.id & GZVM_REG_SIZE_MASK) >> GZVM_REG_SIZE_SHIFT) bytes
+ */
+#define GZVM_REG_SIZE_SHIFT	52
+#define GZVM_REG_SIZE_MASK	0x00f0000000000000ULL
+
+#define GZVM_REG_SIZE_U8	0x0000000000000000ULL
+#define GZVM_REG_SIZE_U16	0x0010000000000000ULL
+#define GZVM_REG_SIZE_U32	0x0020000000000000ULL
+#define GZVM_REG_SIZE_U64	0x0030000000000000ULL
+#define GZVM_REG_SIZE_U128	0x0040000000000000ULL
+#define GZVM_REG_SIZE_U256	0x0050000000000000ULL
+#define GZVM_REG_SIZE_U512	0x0060000000000000ULL
+#define GZVM_REG_SIZE_U1024	0x0070000000000000ULL
+#define GZVM_REG_SIZE_U2048	0x0080000000000000ULL
+
+/* Register type definitions */
+#define GZVM_REG_TYPE_SHIFT	16
+/* Register type: general purpose */
+#define GZVM_REG_TYPE_GENERAL	(0x10 << GZVM_REG_TYPE_SHIFT)
+
 /* GZVM ioctls */
 #define GZVM_IOC_MAGIC			0x92	/* gz */