nfp: bpf: fix ALU32 high bits clearance bug
NFP BPF JIT compiler is doing a couple of small optimizations when jitting ALU imm instructions, some of these optimizations could save code-gen, for example: A & -1 = A A | 0 = A A ^ 0 = A However, for ALU32, high 32-bit of the 64-bit register should still be cleared according to ISA semantics. Fixes: cd7df56ed3e6 ("nfp: add BPF to NFP code translator") Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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Daniel Borkmann
parent
71c190249f
commit
f036ebd9bf
@ -1291,15 +1291,10 @@ wrp_alu64_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta,
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static int
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wrp_alu32_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta,
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enum alu_op alu_op, bool skip)
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enum alu_op alu_op)
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{
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const struct bpf_insn *insn = &meta->insn;
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if (skip) {
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meta->skip = true;
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return 0;
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}
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wrp_alu_imm(nfp_prog, insn->dst_reg * 2, alu_op, insn->imm);
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wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0);
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@ -2309,7 +2304,7 @@ static int xor_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int xor_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_XOR, !meta->insn.imm);
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_XOR);
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}
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static int and_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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@ -2319,7 +2314,7 @@ static int and_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int and_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_AND, !~meta->insn.imm);
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_AND);
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}
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static int or_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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@ -2329,7 +2324,7 @@ static int or_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int or_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_OR, !meta->insn.imm);
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_OR);
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}
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static int add_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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@ -2339,7 +2334,7 @@ static int add_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int add_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_ADD, !meta->insn.imm);
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_ADD);
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}
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static int sub_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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@ -2349,7 +2344,7 @@ static int sub_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int sub_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_SUB, !meta->insn.imm);
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return wrp_alu32_imm(nfp_prog, meta, ALU_OP_SUB);
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}
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static int mul_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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