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V_01-00-45

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1. Handling of Non S/W path DMA channel abnormal interrupts in Driver and only TI & RI interrupts handled in FW.
2. Reading MSI status for checking interrupt status of SW MSI.
This commit is contained in:
TC956X 2022-03-09 20:25:12 +09:00 committed by jianzhou
parent fdc5571751
commit ea14eace3a
4 changed files with 37 additions and 9 deletions
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8
Readme.md
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@ -1,7 +1,7 @@
# Toshiba Electronic Devices & Storage Corporation TC956X PCIe Ethernet Host Driver
Release Date: 25 Feb 2022
Release Date: 09 Mar 2022
Release Version: V_01-00-44 : Limited-tested version
Release Version: V_01-00-45 : Limited-tested version
TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
@ -472,3 +472,7 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
1. XPCS module is re-initialized after link-up as MACxPONRST is asserted during link-down.
2. Disable Rx side EEE LPI before configuring Rx Parser (FRP). Enable the same after Rx Parser configuration.
## TC956X_Host_Driver_20220309_V_01-00-45:
1. Handling of Non S/W path DMA channel abnormal interrupts in Driver and only TI & RI interrupts handled in FW.
2. Reading MSI status for checking interrupt status of SW MSI.

4
tc956x_pci.c
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@ -147,6 +147,8 @@
* VERSION : 01-00-43
* 25 Feb 2022 : 1. Version update
* VERSION : 01-00-44
* 09 Mar 2022 : 1. Version update
* VERSION : 01-00-45
*/
#include <linux/clk-provider.h>
@ -211,7 +213,7 @@ static unsigned int mac1_txq1_size = TX_QUEUE1_SIZE;
unsigned int mac0_en_lp_pause_frame_cnt = DISABLE;
unsigned int mac1_en_lp_pause_frame_cnt = DISABLE;
static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 4, 4};
static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 4, 5};
static int tc956xmac_pm_usage_counter; /* Device Usage Counter */
struct mutex tc956x_pm_suspend_lock; /* This mutex is shared between all available EMAC ports. */

4
tc956xmac.h
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@ -137,6 +137,8 @@
* VERSION : 01-00-43
* 25 Feb 2022 : 1. Version update.
* VERSION : 01-00-44
* 09 Mar 2022 : 1. Version update
* VERSION : 01-00-45
*/
#ifndef __TC956XMAC_H__
@ -192,7 +194,7 @@
#define IRQ_DEV_NAME(x) (((x) == RM_PF0_ID) ? ("eth0") : ("eth1"))
#define WOL_IRQ_DEV_NAME(x) (((x) == RM_PF0_ID) ? ("eth0_wol") : ("eth1_wol"))
#define DRV_MODULE_VERSION "V_01-00-44"
#define DRV_MODULE_VERSION "V_01-00-45"
#define TC956X_FW_MAX_SIZE (64*1024)
#define ATR_AXI4_SLV_BASE 0x0800

30
tc956xmac_main.c
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@ -112,6 +112,9 @@
* 25 Feb 2022 : 1. XPCS module is re-initialized after link-up as MACxPONRST is asserted during link-down.
* 2. Disable Rx side EEE LPI before configuring Rx Parser (FRP). Enable the same after Rx Parser configuration.
* VERSION : 01-00-44
* 09 Mar 2022 : 1. Handling of Non S/W path DMA channel abnormal interrupts in Driver and only TI & RI interrupts handled in FW.
* 2. Reading MSI status for checking interrupt status of SW MSI.
* VERSION : 01-00-45
*/
#include <linux/clk.h>
@ -6683,12 +6686,28 @@ static irqreturn_t tc956xmac_interrupt(int irq, void *dev_id)
/* Checking if any RBUs occurred and updating the statistics corresponding to channel */
for (queue = 0; queue < queues_count; queue++) {
uiIntSts = readl(priv->ioaddr + XGMAC_DMA_CH_STATUS(queue));
if(uiIntSts & XGMAC_RBU) {
priv->xstats.rx_buf_unav_irq[queue]++;
uiIntclr |= XGMAC_RBU;
/* Assuming DMA Tx and Rx channels are used as pairs */
if ((priv->plat->tx_dma_ch_owner[queue] != USE_IN_TC956X_SW) ||
(priv->plat->rx_dma_ch_owner[queue] != USE_IN_TC956X_SW)) {
uiIntSts = readl(priv->ioaddr + XGMAC_DMA_CH_STATUS(queue));
/* Handling Abnormal interrupts of NON S/W path, TI & RI are handled in FW */
if (unlikely(uiIntSts & XGMAC_AIS)) {
if (unlikely(uiIntSts & XGMAC_RBU)) {
priv->xstats.rx_buf_unav_irq[queue]++;
uiIntclr |= XGMAC_RBU;
}
if (unlikely(uiIntSts & XGMAC_TPS)) {
priv->xstats.tx_process_stopped_irq[queue]++;
uiIntclr |= XGMAC_TPS;
}
if (unlikely(uiIntSts & XGMAC_FBE)) {
priv->xstats.fatal_bus_error_irq[queue]++;
uiIntclr |= XGMAC_FBE;
}
uiIntclr |= XGMAC_AIS;
}
writel(uiIntclr, (priv->ioaddr + XGMAC_DMA_CH_STATUS(queue)));
}
writel(uiIntclr, (priv->ioaddr + XGMAC_DMA_CH_STATUS(queue)));
}
/* To handle GMAC own interrupts */
@ -6751,6 +6770,7 @@ static irqreturn_t tc956xmac_interrupt(int irq, void *dev_id)
writel(val, priv->ioaddr + TC956X_MSI_OUT_EN_OFFSET(priv->port_num)); /* MSI_OUT_EN: Writing to disable MAC Ext Interrupt*/
}
#ifdef TC956X_SW_MSI
val = readl(priv->ioaddr + TC956X_MSI_INT_STS_OFFSET(priv->port_num));
if (val & TC956X_SW_MSI_INT) {
//DBGPR_FUNC(priv->device, "%s SW MSI INT STS[%08x]\n", __func__, val);