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Merge "dt-bindings: Add dt includes for various dt nodes"

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qctecmdr
2023-03-24 11:06:56 -07:00
committed by Gerrit - the friendly Code Review server
parent 5cfe44b2ac d9fd363cc7
commit e43fd3032e
7 changed files with 4305 additions and 0 deletions
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include/dt-bindings/clock/qcom,gcc-direwolf.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL2 2
#define GCC_GPLL4 3
#define GCC_GPLL7 4
#define GCC_GPLL8 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7
#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8
#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9
#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10
#define GCC_AGGRE_UFS_CARD_AXI_CLK 11
#define GCC_AGGRE_UFS_PHY_AXI_CLK 12
#define GCC_AGGRE_USB3_MP_AXI_CLK 13
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14
#define GCC_AGGRE_USB3_SEC_AXI_CLK 15
#define GCC_AGGRE_USB4_1_AXI_CLK 16
#define GCC_AGGRE_USB4_AXI_CLK 17
#define GCC_AGGRE_USB_NOC_AXI_CLK 18
#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19
#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20
#define GCC_AHB2PHY0_CLK 21
#define GCC_AHB2PHY2_CLK 22
#define GCC_BOOT_ROM_AHB_CLK 23
#define GCC_CAMERA_AHB_CLK 24
#define GCC_CAMERA_HF_AXI_CLK 25
#define GCC_CAMERA_SF_AXI_CLK 26
#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27
#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28
#define GCC_CAMERA_THROTTLE_XO_CLK 29
#define GCC_CAMERA_XO_CLK 30
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33
#define GCC_CNOC_PCIE0_TUNNEL_CLK 34
#define GCC_CNOC_PCIE1_TUNNEL_CLK 35
#define GCC_CNOC_PCIE4_QX_CLK 36
#define GCC_DDRSS_GPU_AXI_CLK 37
#define GCC_DDRSS_PCIE_SF_TBU_CLK 38
#define GCC_DISP1_AHB_CLK 39
#define GCC_DISP1_HF_AXI_CLK 40
#define GCC_DISP1_SF_AXI_CLK 41
#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42
#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43
#define GCC_DISP1_XO_CLK 44
#define GCC_DISP_AHB_CLK 45
#define GCC_DISP_HF_AXI_CLK 46
#define GCC_DISP_SF_AXI_CLK 47
#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48
#define GCC_DISP_THROTTLE_RT_AXI_CLK 49
#define GCC_DISP_XO_CLK 50
#define GCC_EMAC0_AXI_CLK 51
#define GCC_EMAC0_PTP_CLK 52
#define GCC_EMAC0_PTP_CLK_SRC 53
#define GCC_EMAC0_RGMII_CLK 54
#define GCC_EMAC0_RGMII_CLK_SRC 55
#define GCC_EMAC0_SLV_AHB_CLK 56
#define GCC_EMAC1_AXI_CLK 57
#define GCC_EMAC1_PTP_CLK 58
#define GCC_EMAC1_PTP_CLK_SRC 59
#define GCC_EMAC1_RGMII_CLK 60
#define GCC_EMAC1_RGMII_CLK_SRC 61
#define GCC_EMAC1_SLV_AHB_CLK 62
#define GCC_GP1_CLK 63
#define GCC_GP1_CLK_SRC 64
#define GCC_GP2_CLK 65
#define GCC_GP2_CLK_SRC 66
#define GCC_GP3_CLK 67
#define GCC_GP3_CLK_SRC 68
#define GCC_GP4_CLK 69
#define GCC_GP4_CLK_SRC 70
#define GCC_GP5_CLK 71
#define GCC_GP5_CLK_SRC 72
#define GCC_GPU_CFG_AHB_CLK 73
#define GCC_GPU_GPLL0_CLK_SRC 74
#define GCC_GPU_GPLL0_DIV_CLK_SRC 75
#define GCC_GPU_IREF_EN 76
#define GCC_GPU_MEMNOC_GFX_CLK 77
#define GCC_GPU_SNOC_DVM_GFX_CLK 78
#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79
#define GCC_GPU_TCU_THROTTLE_CLK 80
#define GCC_PCIE0_PHY_RCHNG_CLK 81
#define GCC_PCIE1_PHY_RCHNG_CLK 82
#define GCC_PCIE2A_PHY_RCHNG_CLK 83
#define GCC_PCIE2B_PHY_RCHNG_CLK 84
#define GCC_PCIE3A_PHY_RCHNG_CLK 85
#define GCC_PCIE3B_PHY_RCHNG_CLK 86
#define GCC_PCIE4_PHY_RCHNG_CLK 87
#define GCC_PCIE_0_AUX_CLK 88
#define GCC_PCIE_0_AUX_CLK_SRC 89
#define GCC_PCIE_0_CFG_AHB_CLK 90
#define GCC_PCIE_0_MSTR_AXI_CLK 91
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92
#define GCC_PCIE_0_PIPE_CLK 93
#define GCC_PCIE_0_SLV_AXI_CLK 94
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95
#define GCC_PCIE_1_AUX_CLK 96
#define GCC_PCIE_1_AUX_CLK_SRC 97
#define GCC_PCIE_1_CFG_AHB_CLK 98
#define GCC_PCIE_1_MSTR_AXI_CLK 99
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100
#define GCC_PCIE_1_PIPE_CLK 101
#define GCC_PCIE_1_SLV_AXI_CLK 102
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103
#define GCC_PCIE_2A2B_CLKREF_CLK 104
#define GCC_PCIE_2A_AUX_CLK 105
#define GCC_PCIE_2A_AUX_CLK_SRC 106
#define GCC_PCIE_2A_CFG_AHB_CLK 107
#define GCC_PCIE_2A_MSTR_AXI_CLK 108
#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109
#define GCC_PCIE_2A_PIPE_CLK 110
#define GCC_PCIE_2A_PIPE_CLK_SRC 111
#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112
#define GCC_PCIE_2A_PIPEDIV2_CLK 113
#define GCC_PCIE_2A_SLV_AXI_CLK 114
#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115
#define GCC_PCIE_2B_AUX_CLK 116
#define GCC_PCIE_2B_AUX_CLK_SRC 117
#define GCC_PCIE_2B_CFG_AHB_CLK 118
#define GCC_PCIE_2B_MSTR_AXI_CLK 119
#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120
#define GCC_PCIE_2B_PIPE_CLK 121
#define GCC_PCIE_2B_PIPE_CLK_SRC 122
#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123
#define GCC_PCIE_2B_PIPEDIV2_CLK 124
#define GCC_PCIE_2B_SLV_AXI_CLK 125
#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126
#define GCC_PCIE_3A3B_CLKREF_CLK 127
#define GCC_PCIE_3A_AUX_CLK 128
#define GCC_PCIE_3A_AUX_CLK_SRC 129
#define GCC_PCIE_3A_CFG_AHB_CLK 130
#define GCC_PCIE_3A_MSTR_AXI_CLK 131
#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132
#define GCC_PCIE_3A_PIPE_CLK 133
#define GCC_PCIE_3A_PIPE_CLK_SRC 134
#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135
#define GCC_PCIE_3A_PIPEDIV2_CLK 136
#define GCC_PCIE_3A_SLV_AXI_CLK 137
#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138
#define GCC_PCIE_3B_AUX_CLK 139
#define GCC_PCIE_3B_AUX_CLK_SRC 140
#define GCC_PCIE_3B_CFG_AHB_CLK 141
#define GCC_PCIE_3B_MSTR_AXI_CLK 142
#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143
#define GCC_PCIE_3B_PIPE_CLK 144
#define GCC_PCIE_3B_PIPE_CLK_SRC 145
#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146
#define GCC_PCIE_3B_PIPEDIV2_CLK 147
#define GCC_PCIE_3B_SLV_AXI_CLK 148
#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149
#define GCC_PCIE_4_AUX_CLK 150
#define GCC_PCIE_4_AUX_CLK_SRC 151
#define GCC_PCIE_4_CFG_AHB_CLK 152
#define GCC_PCIE_4_CLKREF_CLK 153
#define GCC_PCIE_4_MSTR_AXI_CLK 154
#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155
#define GCC_PCIE_4_PIPE_CLK 156
#define GCC_PCIE_4_PIPE_CLK_SRC 157
#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158
#define GCC_PCIE_4_PIPEDIV2_CLK 159
#define GCC_PCIE_4_SLV_AXI_CLK 160
#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161
#define GCC_PCIE_RSCC_AHB_CLK 162
#define GCC_PCIE_RSCC_XO_CLK 163
#define GCC_PCIE_RSCC_XO_CLK_SRC 164
#define GCC_PCIE_THROTTLE_CFG_CLK 165
#define GCC_PDM2_CLK 166
#define GCC_PDM2_CLK_SRC 167
#define GCC_PDM_AHB_CLK 168
#define GCC_PDM_XO4_CLK 169
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170
#define GCC_QMIP_CAMERA_RT_AHB_CLK 171
#define GCC_QMIP_DISP1_AHB_CLK 172
#define GCC_QMIP_DISP1_ROT_AHB_CLK 173
#define GCC_QMIP_DISP_AHB_CLK 174
#define GCC_QMIP_DISP_ROT_AHB_CLK 175
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178
#define GCC_QUPV3_WRAP0_CORE_CLK 179
#define GCC_QUPV3_WRAP0_QSPI0_CLK 180
#define GCC_QUPV3_WRAP0_S0_CLK 181
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182
#define GCC_QUPV3_WRAP0_S1_CLK 183
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184
#define GCC_QUPV3_WRAP0_S2_CLK 185
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186
#define GCC_QUPV3_WRAP0_S3_CLK 187
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188
#define GCC_QUPV3_WRAP0_S4_CLK 189
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190
#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191
#define GCC_QUPV3_WRAP0_S5_CLK 192
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193
#define GCC_QUPV3_WRAP0_S6_CLK 194
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195
#define GCC_QUPV3_WRAP0_S7_CLK 196
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198
#define GCC_QUPV3_WRAP1_CORE_CLK 199
#define GCC_QUPV3_WRAP1_QSPI0_CLK 200
#define GCC_QUPV3_WRAP1_S0_CLK 201
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202
#define GCC_QUPV3_WRAP1_S1_CLK 203
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204
#define GCC_QUPV3_WRAP1_S2_CLK 205
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206
#define GCC_QUPV3_WRAP1_S3_CLK 207
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208
#define GCC_QUPV3_WRAP1_S4_CLK 209
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210
#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211
#define GCC_QUPV3_WRAP1_S5_CLK 212
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213
#define GCC_QUPV3_WRAP1_S6_CLK 214
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215
#define GCC_QUPV3_WRAP1_S7_CLK 216
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218
#define GCC_QUPV3_WRAP2_CORE_CLK 219
#define GCC_QUPV3_WRAP2_QSPI0_CLK 220
#define GCC_QUPV3_WRAP2_S0_CLK 221
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222
#define GCC_QUPV3_WRAP2_S1_CLK 223
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224
#define GCC_QUPV3_WRAP2_S2_CLK 225
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226
#define GCC_QUPV3_WRAP2_S3_CLK 227
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228
#define GCC_QUPV3_WRAP2_S4_CLK 229
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230
#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231
#define GCC_QUPV3_WRAP2_S5_CLK 232
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233
#define GCC_QUPV3_WRAP2_S6_CLK 234
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235
#define GCC_QUPV3_WRAP2_S7_CLK 236
#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243
#define GCC_SDCC2_AHB_CLK 244
#define GCC_SDCC2_APPS_CLK 245
#define GCC_SDCC2_APPS_CLK_SRC 246
#define GCC_SDCC4_AHB_CLK 247
#define GCC_SDCC4_APPS_CLK 248
#define GCC_SDCC4_APPS_CLK_SRC 249
#define GCC_SYS_NOC_USB_AXI_CLK 250
#define GCC_UFS_1_CARD_CLKREF_CLK 251
#define GCC_UFS_CARD_AHB_CLK 252
#define GCC_UFS_CARD_AXI_CLK 253
#define GCC_UFS_CARD_AXI_CLK_SRC 254
#define GCC_UFS_CARD_CLKREF_CLK 255
#define GCC_UFS_CARD_ICE_CORE_CLK 256
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257
#define GCC_UFS_CARD_PHY_AUX_CLK 258
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267
#define GCC_UFS_PHY_AHB_CLK 268
#define GCC_UFS_PHY_AXI_CLK 269
#define GCC_UFS_PHY_AXI_CLK_SRC 270
#define GCC_UFS_PHY_ICE_CORE_CLK 271
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272
#define GCC_UFS_PHY_PHY_AUX_CLK 273
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282
#define GCC_UFS_REF_CLKREF_CLK 283
#define GCC_USB2_HS0_CLKREF_CLK 284
#define GCC_USB2_HS1_CLKREF_CLK 285
#define GCC_USB2_HS2_CLKREF_CLK 286
#define GCC_USB2_HS3_CLKREF_CLK 287
#define GCC_USB30_MP_MASTER_CLK 288
#define GCC_USB30_MP_MASTER_CLK_SRC 289
#define GCC_USB30_MP_MOCK_UTMI_CLK 290
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291
#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292
#define GCC_USB30_MP_SLEEP_CLK 293
#define GCC_USB30_PRIM_MASTER_CLK 294
#define GCC_USB30_PRIM_MASTER_CLK_SRC 295
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298
#define GCC_USB30_PRIM_SLEEP_CLK 299
#define GCC_USB30_SEC_MASTER_CLK 300
#define GCC_USB30_SEC_MASTER_CLK_SRC 301
#define GCC_USB30_SEC_MOCK_UTMI_CLK 302
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304
#define GCC_USB30_SEC_SLEEP_CLK 305
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307
#define GCC_USB3_MP0_CLKREF_CLK 308
#define GCC_USB3_MP1_CLKREF_CLK 309
#define GCC_USB3_MP_PHY_AUX_CLK 310
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311
#define GCC_USB3_MP_PHY_COM_AUX_CLK 312
#define GCC_USB3_MP_PHY_PIPE_0_CLK 313
#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314
#define GCC_USB3_MP_PHY_PIPE_1_CLK 315
#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316
#define GCC_USB3_PRIM_PHY_AUX_CLK 317
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319
#define GCC_USB3_PRIM_PHY_PIPE_CLK 320
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321
#define GCC_USB3_SEC_PHY_AUX_CLK 322
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324
#define GCC_USB3_SEC_PHY_PIPE_CLK 325
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326
#define GCC_USB4_1_CFG_AHB_CLK 327
#define GCC_USB4_1_DP_CLK 328
#define GCC_USB4_1_MASTER_CLK 329
#define GCC_USB4_1_MASTER_CLK_SRC 330
#define GCC_USB4_1_PHY_DP_CLK_SRC 331
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334
#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336
#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337
#define GCC_USB4_1_PHY_RX0_CLK 338
#define GCC_USB4_1_PHY_RX0_CLK_SRC 339
#define GCC_USB4_1_PHY_RX1_CLK 340
#define GCC_USB4_1_PHY_RX1_CLK_SRC 341
#define GCC_USB4_1_PHY_SYS_CLK_SRC 342
#define GCC_USB4_1_PHY_USB_PIPE_CLK 343
#define GCC_USB4_1_SB_IF_CLK 344
#define GCC_USB4_1_SB_IF_CLK_SRC 345
#define GCC_USB4_1_SYS_CLK 346
#define GCC_USB4_1_TMU_CLK 347
#define GCC_USB4_1_TMU_CLK_SRC 348
#define GCC_USB4_CFG_AHB_CLK 349
#define GCC_USB4_CLKREF_CLK 350
#define GCC_USB4_DP_CLK 351
#define GCC_USB4_EUD_CLKREF_CLK 352
#define GCC_USB4_MASTER_CLK 353
#define GCC_USB4_MASTER_CLK_SRC 354
#define GCC_USB4_PHY_DP_CLK_SRC 355
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356
#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357
#define GCC_USB4_PHY_PCIE_PIPE_CLK 358
#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359
#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360
#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361
#define GCC_USB4_PHY_RX0_CLK 362
#define GCC_USB4_PHY_RX0_CLK_SRC 363
#define GCC_USB4_PHY_RX1_CLK 364
#define GCC_USB4_PHY_RX1_CLK_SRC 365
#define GCC_USB4_PHY_SYS_CLK_SRC 366
#define GCC_USB4_PHY_USB_PIPE_CLK 367
#define GCC_USB4_SB_IF_CLK 368
#define GCC_USB4_SB_IF_CLK_SRC 369
#define GCC_USB4_SYS_CLK 370
#define GCC_USB4_TMU_CLK 371
#define GCC_USB4_TMU_CLK_SRC 372
#define GCC_VIDEO_AHB_CLK 373
#define GCC_VIDEO_AXI0_CLK 374
#define GCC_VIDEO_AXI1_CLK 375
#define GCC_VIDEO_CVP_THROTTLE_CLK 376
#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377
#define GCC_VIDEO_XO_CLK 378
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388
/* GCC resets */
#define GCC_EMAC0_BCR 0
#define GCC_EMAC1_BCR 1
#define GCC_PCIE_0_LINK_DOWN_BCR 2
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3
#define GCC_PCIE_0_PHY_BCR 4
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5
#define GCC_PCIE_0_TUNNEL_BCR 6
#define GCC_PCIE_1_LINK_DOWN_BCR 7
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_1_PHY_BCR 9
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10
#define GCC_PCIE_1_TUNNEL_BCR 11
#define GCC_PCIE_2A_BCR 12
#define GCC_PCIE_2A_LINK_DOWN_BCR 13
#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14
#define GCC_PCIE_2A_PHY_BCR 15
#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16
#define GCC_PCIE_2B_BCR 17
#define GCC_PCIE_2B_LINK_DOWN_BCR 18
#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19
#define GCC_PCIE_2B_PHY_BCR 20
#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21
#define GCC_PCIE_3A_BCR 22
#define GCC_PCIE_3A_LINK_DOWN_BCR 23
#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24
#define GCC_PCIE_3A_PHY_BCR 25
#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26
#define GCC_PCIE_3B_BCR 27
#define GCC_PCIE_3B_LINK_DOWN_BCR 28
#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29
#define GCC_PCIE_3B_PHY_BCR 30
#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31
#define GCC_PCIE_4_BCR 32
#define GCC_PCIE_4_LINK_DOWN_BCR 33
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34
#define GCC_PCIE_4_PHY_BCR 35
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36
#define GCC_PCIE_PHY_CFG_AHB_BCR 37
#define GCC_PCIE_PHY_COM_BCR 38
#define GCC_PCIE_RSCC_BCR 39
#define GCC_QUSB2PHY_HS0_MP_BCR 40
#define GCC_QUSB2PHY_HS1_MP_BCR 41
#define GCC_QUSB2PHY_HS2_MP_BCR 42
#define GCC_QUSB2PHY_HS3_MP_BCR 43
#define GCC_QUSB2PHY_PRIM_BCR 44
#define GCC_QUSB2PHY_SEC_BCR 45
#define GCC_SDCC2_BCR 46
#define GCC_SDCC4_BCR 47
#define GCC_UFS_CARD_BCR 48
#define GCC_UFS_PHY_BCR 49
#define GCC_USB2_PHY_PRIM_BCR 50
#define GCC_USB2_PHY_SEC_BCR 51
#define GCC_USB30_MP_BCR 52
#define GCC_USB30_PRIM_BCR 53
#define GCC_USB30_SEC_BCR 54
#define GCC_USB3_DP_PHY_PRIM_BCR 55
#define GCC_USB3_DP_PHY_SEC_BCR 56
#define GCC_USB3_PHY_PRIM_BCR 57
#define GCC_USB3_PHY_SEC_BCR 58
#define GCC_USB3_UNIPHY_MP0_BCR 59
#define GCC_USB3_UNIPHY_MP1_BCR 60
#define GCC_USB3PHY_PHY_PRIM_BCR 61
#define GCC_USB3PHY_PHY_SEC_BCR 62
#define GCC_USB3UNIPHY_PHY_MP0_BCR 63
#define GCC_USB3UNIPHY_PHY_MP1_BCR 64
#define GCC_USB4_1_BCR 65
#define GCC_USB4_1_DP_PHY_PRIM_BCR 66
#define GCC_USB4_1_DPPHY_AUX_BCR 67
#define GCC_USB4_1_PHY_PRIM_BCR 68
#define GCC_USB4_BCR 69
#define GCC_USB4_DP_PHY_PRIM_BCR 70
#define GCC_USB4_DPPHY_AUX_BCR 71
#define GCC_USB4_PHY_PRIM_BCR 72
#define GCC_USB4PHY_1_PHY_PRIM_BCR 73
#define GCC_USB4PHY_PHY_PRIM_BCR 74
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75
#define GCC_VIDEO_BCR 76
#define GCC_VIDEO_AXI0_CLK_ARES 77
#define GCC_VIDEO_AXI1_CLK_ARES 78
#endif

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include/dt-bindings/clock/qcom,gcc-lemans.h Normal file
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@ -0,0 +1,298 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LEMANS_H
#define _DT_BINDINGS_CLK_QCOM_GCC_LEMANS_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL1 2
#define GCC_GPLL4 3
#define GCC_GPLL5 4
#define GCC_GPLL7 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7
#define GCC_AGGRE_UFS_CARD_AXI_CLK 8
#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11
#define GCC_AGGRE_USB3_SEC_AXI_CLK 12
#define GCC_AHB2PHY0_CLK 13
#define GCC_AHB2PHY2_CLK 14
#define GCC_AHB2PHY3_CLK 15
#define GCC_BOOT_ROM_AHB_CLK 16
#define GCC_CAMERA_AHB_CLK 17
#define GCC_CAMERA_HF_AXI_CLK 18
#define GCC_CAMERA_SF_AXI_CLK 19
#define GCC_CAMERA_THROTTLE_XO_CLK 20
#define GCC_CAMERA_XO_CLK 21
#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24
#define GCC_DDRSS_GPU_AXI_CLK 25
#define GCC_DISP1_AHB_CLK 26
#define GCC_DISP1_HF_AXI_CLK 27
#define GCC_DISP1_XO_CLK 28
#define GCC_DISP_AHB_CLK 29
#define GCC_DISP_HF_AXI_CLK 30
#define GCC_DISP_XO_CLK 31
#define GCC_EDP_REF_CLKREF_EN 32
#define GCC_EMAC0_AXI_CLK 33
#define GCC_EMAC0_PHY_AUX_CLK 34
#define GCC_EMAC0_PHY_AUX_CLK_SRC 35
#define GCC_EMAC0_PTP_CLK 36
#define GCC_EMAC0_PTP_CLK_SRC 37
#define GCC_EMAC0_RGMII_CLK 38
#define GCC_EMAC0_RGMII_CLK_SRC 39
#define GCC_EMAC0_SLV_AHB_CLK 40
#define GCC_EMAC1_AXI_CLK 41
#define GCC_EMAC1_PHY_AUX_CLK 42
#define GCC_EMAC1_PHY_AUX_CLK_SRC 43
#define GCC_EMAC1_PTP_CLK 44
#define GCC_EMAC1_PTP_CLK_SRC 45
#define GCC_EMAC1_RGMII_CLK 46
#define GCC_EMAC1_RGMII_CLK_SRC 47
#define GCC_EMAC1_SLV_AHB_CLK 48
#define GCC_GP1_CLK 49
#define GCC_GP1_CLK_SRC 50
#define GCC_GP2_CLK 51
#define GCC_GP2_CLK_SRC 52
#define GCC_GP3_CLK 53
#define GCC_GP3_CLK_SRC 54
#define GCC_GP4_CLK 55
#define GCC_GP4_CLK_SRC 56
#define GCC_GP5_CLK 57
#define GCC_GP5_CLK_SRC 58
#define GCC_GPU_CFG_AHB_CLK 59
#define GCC_GPU_GPLL0_CLK_SRC 60
#define GCC_GPU_GPLL0_DIV_CLK_SRC 61
#define GCC_GPU_MEMNOC_GFX_CLK 62
#define GCC_GPU_SNOC_DVM_GFX_CLK 63
#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64
#define GCC_GPU_TCU_THROTTLE_CLK 65
#define GCC_PCIE_0_AUX_CLK 66
#define GCC_PCIE_0_AUX_CLK_SRC 67
#define GCC_PCIE_0_CFG_AHB_CLK 68
#define GCC_PCIE_0_MSTR_AXI_CLK 69
#define GCC_PCIE_0_PHY_AUX_CLK 70
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71
#define GCC_PCIE_0_PHY_RCHNG_CLK 72
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73
#define GCC_PCIE_0_PIPE_CLK 74
#define GCC_PCIE_0_PIPE_CLK_SRC 75
#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76
#define GCC_PCIE_0_PIPEDIV2_CLK 77
#define GCC_PCIE_0_SLV_AXI_CLK 78
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79
#define GCC_PCIE_1_AUX_CLK 80
#define GCC_PCIE_1_AUX_CLK_SRC 81
#define GCC_PCIE_1_CFG_AHB_CLK 82
#define GCC_PCIE_1_MSTR_AXI_CLK 83
#define GCC_PCIE_1_PHY_AUX_CLK 84
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85
#define GCC_PCIE_1_PHY_RCHNG_CLK 86
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87
#define GCC_PCIE_1_PIPE_CLK 88
#define GCC_PCIE_1_PIPE_CLK_SRC 89
#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90
#define GCC_PCIE_1_PIPEDIV2_CLK 91
#define GCC_PCIE_1_SLV_AXI_CLK 92
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93
#define GCC_PCIE_CLKREF_EN 94
#define GCC_PCIE_THROTTLE_CFG_CLK 95
#define GCC_PDM2_CLK 96
#define GCC_PDM2_CLK_SRC 97
#define GCC_PDM_AHB_CLK 98
#define GCC_PDM_XO4_CLK 99
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100
#define GCC_QMIP_CAMERA_RT_AHB_CLK 101
#define GCC_QMIP_DISP1_AHB_CLK 102
#define GCC_QMIP_DISP1_ROT_AHB_CLK 103
#define GCC_QMIP_DISP_AHB_CLK 104
#define GCC_QMIP_DISP_ROT_AHB_CLK 105
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107
#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109
#define GCC_QUPV3_WRAP0_CORE_CLK 110
#define GCC_QUPV3_WRAP0_S0_CLK 111
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112
#define GCC_QUPV3_WRAP0_S1_CLK 113
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114
#define GCC_QUPV3_WRAP0_S2_CLK 115
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116
#define GCC_QUPV3_WRAP0_S3_CLK 117
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118
#define GCC_QUPV3_WRAP0_S4_CLK 119
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120
#define GCC_QUPV3_WRAP0_S5_CLK 121
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122
#define GCC_QUPV3_WRAP0_S6_CLK 123
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125
#define GCC_QUPV3_WRAP1_CORE_CLK 126
#define GCC_QUPV3_WRAP1_S0_CLK 127
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128
#define GCC_QUPV3_WRAP1_S1_CLK 129
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130
#define GCC_QUPV3_WRAP1_S2_CLK 131
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132
#define GCC_QUPV3_WRAP1_S3_CLK 133
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134
#define GCC_QUPV3_WRAP1_S4_CLK 135
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136
#define GCC_QUPV3_WRAP1_S5_CLK 137
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138
#define GCC_QUPV3_WRAP1_S6_CLK 139
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141
#define GCC_QUPV3_WRAP2_CORE_CLK 142
#define GCC_QUPV3_WRAP2_S0_CLK 143
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144
#define GCC_QUPV3_WRAP2_S1_CLK 145
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146
#define GCC_QUPV3_WRAP2_S2_CLK 147
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148
#define GCC_QUPV3_WRAP2_S3_CLK 149
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150
#define GCC_QUPV3_WRAP2_S4_CLK 151
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152
#define GCC_QUPV3_WRAP2_S5_CLK 153
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154
#define GCC_QUPV3_WRAP2_S6_CLK 155
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157
#define GCC_QUPV3_WRAP3_CORE_CLK 158
#define GCC_QUPV3_WRAP3_QSPI_CLK 159
#define GCC_QUPV3_WRAP3_S0_CLK 160
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161
#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170
#define GCC_SDCC1_AHB_CLK 171
#define GCC_SDCC1_APPS_CLK 172
#define GCC_SDCC1_APPS_CLK_SRC 173
#define GCC_SDCC1_ICE_CORE_CLK 174
#define GCC_SDCC1_ICE_CORE_CLK_SRC 175
#define GCC_SGMI_CLKREF_EN 176
#define GCC_TSCSS_AHB_CLK 177
#define GCC_TSCSS_CNTR_CLK_SRC 178
#define GCC_TSCSS_ETU_CLK 179
#define GCC_TSCSS_GLOBAL_CNTR_CLK 180
#define GCC_UFS_CARD_AHB_CLK 181
#define GCC_UFS_CARD_AXI_CLK 182
#define GCC_UFS_CARD_AXI_CLK_SRC 183
#define GCC_UFS_CARD_ICE_CORE_CLK 184
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185
#define GCC_UFS_CARD_PHY_AUX_CLK 186
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195
#define GCC_UFS_PHY_AHB_CLK 196
#define GCC_UFS_PHY_AXI_CLK 197
#define GCC_UFS_PHY_AXI_CLK_SRC 198
#define GCC_UFS_PHY_ICE_CORE_CLK 199
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200
#define GCC_UFS_PHY_PHY_AUX_CLK 201
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210
#define GCC_USB20_MASTER_CLK 211
#define GCC_USB20_MASTER_CLK_SRC 212
#define GCC_USB20_MOCK_UTMI_CLK 213
#define GCC_USB20_MOCK_UTMI_CLK_SRC 214
#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215
#define GCC_USB20_SLEEP_CLK 216
#define GCC_USB30_PRIM_MASTER_CLK 217
#define GCC_USB30_PRIM_MASTER_CLK_SRC 218
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221
#define GCC_USB30_PRIM_SLEEP_CLK 222
#define GCC_USB30_SEC_MASTER_CLK 223
#define GCC_USB30_SEC_MASTER_CLK_SRC 224
#define GCC_USB30_SEC_MOCK_UTMI_CLK 225
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227
#define GCC_USB30_SEC_SLEEP_CLK 228
#define GCC_USB3_PRIM_PHY_AUX_CLK 229
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231
#define GCC_USB3_PRIM_PHY_PIPE_CLK 232
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233
#define GCC_USB3_SEC_PHY_AUX_CLK 234
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236
#define GCC_USB3_SEC_PHY_PIPE_CLK 237
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238
#define GCC_USB_CLKREF_EN 239
#define GCC_VIDEO_AHB_CLK 240
#define GCC_VIDEO_AXI0_CLK 241
#define GCC_VIDEO_AXI1_CLK 242
#define GCC_VIDEO_XO_CLK 243
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248
/* GCC resets */
#define GCC_EMAC0_BCR 0
#define GCC_EMAC1_BCR 1
#define GCC_PCIE_0_BCR 2
#define GCC_PCIE_0_LINK_DOWN_BCR 3
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 4
#define GCC_PCIE_0_PHY_BCR 5
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_1_BCR 7
#define GCC_PCIE_1_LINK_DOWN_BCR 8
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 9
#define GCC_PCIE_1_PHY_BCR 10
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 11
#define GCC_PCIE_RSCC_BCR 12
#define GCC_SDCC1_BCR 13
#define GCC_UFS_CARD_BCR 14
#define GCC_UFS_PHY_BCR 15
#define GCC_USB20_PRIM_BCR 16
#define GCC_USB2_PHY_PRIM_BCR 17
#define GCC_USB2_PHY_SEC_BCR 18
#define GCC_USB30_PRIM_BCR 19
#define GCC_USB30_SEC_BCR 20
#define GCC_USB3_DP_PHY_PRIM_BCR 21
#define GCC_USB3_DP_PHY_SEC_BCR 22
#define GCC_USB3_PHY_PRIM_BCR 23
#define GCC_USB3_PHY_SEC_BCR 24
#define GCC_USB3_PHY_TERT_BCR 25
#define GCC_USB3_UNIPHY_MP0_BCR 26
#define GCC_USB3_UNIPHY_MP1_BCR 27
#define GCC_USB3PHY_PHY_PRIM_BCR 28
#define GCC_USB3PHY_PHY_SEC_BCR 29
#define GCC_USB3UNIPHY_PHY_MP0_BCR 30
#define GCC_USB3UNIPHY_PHY_MP1_BCR 31
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 32
#define GCC_VIDEO_BCR 33
#define GCC_VIDEO_AXI0_CLK_ARES 34
#define GCC_VIDEO_AXI1_CLK_ARES 35
#endif

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include/dt-bindings/clock/qcom,gcc-sc8180x.h
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@ -2,6 +2,7 @@
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H
@ -246,6 +247,21 @@
#define GCC_PCIE_3_CLKREF_CLK 236
#define GCC_USB3_PRIM_CLKREF_CLK 237
#define GCC_USB3_SEC_CLKREF_CLK 238
#define GPLL9 239
#define GCC_AGGRE_UFS_CARD_2_AXI_CLK 240
#define GCC_CAMERA_AHB_CLK 241
#define GCC_CAMERA_XO_CLK 242
#define GCC_CPUSS_DVM_BUS_CLK 243
#define GCC_CPUSS_GNOC_CLK 244
#define GCC_DISP_AHB_CLK 245
#define GCC_DISP_XO_CLK 246
#define GCC_GPU_CFG_AHB_CLK 247
#define GCC_GPU_IREF_CLK 248
#define GCC_NPU_CFG_AHB_CLK 249
#define GCC_UFS_CARD_CLKREF_CLK 250
#define GCC_VIDEO_AHB_CLK 251
#define GCC_VIDEO_XO_CLK 252
#define GCC_UFS_MEM_CLKREF_CLK 254
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1
@ -292,6 +308,10 @@
#define GCC_VIDEO_AXI0_CLK_BCR 42
#define GCC_VIDEO_AXI1_CLK_BCR 43
#define GCC_USB3_DP_PHY_SEC_BCR 44
#define GCC_USB3_UNIPHY_MP0_BCR 45
#define GCC_USB3_UNIPHY_MP1_BCR 46
#define GCC_USB3UNIPHY_PHY_MP0_BCR 47
#define GCC_USB3UNIPHY_PHY_MP1_BCR 48
/* GCC GDSCRs */
#define EMAC_GDSC 0

23
include/dt-bindings/input/qcom,qpnp-power-on.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019,2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_INPUT_QCOM_POWER_ON_H
#define _DT_BINDINGS_INPUT_QCOM_POWER_ON_H
/* PMIC PON peripheral logical power on types: */
#define PON_POWER_ON_TYPE_KPDPWR 0
#define PON_POWER_ON_TYPE_RESIN 1
#define PON_POWER_ON_TYPE_CBLPWR 2
#define PON_POWER_ON_TYPE_KPDPWR_RESIN 3
/* PMIC PON peripheral physical power off types: */
#define PON_POWER_OFF_TYPE_WARM_RESET 0x01
#define PON_POWER_OFF_TYPE_SHUTDOWN 0x04
#define PON_POWER_OFF_TYPE_DVDD_SHUTDOWN 0x05
#define PON_POWER_OFF_TYPE_HARD_RESET 0x07
#define PON_POWER_OFF_TYPE_DVDD_HARD_RESET 0x08
#endif

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include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h Normal file
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include/dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H
#define _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H
/* USB3 Uni PHY register offsets */
/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
#define USB3_UNI_QSERDES_COM_ATB_SEL1 (0x0000 + 0x0000)
#define USB3_UNI_QSERDES_COM_ATB_SEL2 (0x0000 + 0x0004)
#define USB3_UNI_QSERDES_COM_FREQ_UPDATE (0x0000 + 0x0008)
#define USB3_UNI_QSERDES_COM_BG_TIMER (0x0000 + 0x000c)
#define USB3_UNI_QSERDES_COM_SSC_EN_CENTER (0x0000 + 0x0010)
#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER1 (0x0000 + 0x0014)
#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER2 (0x0000 + 0x0018)
#define USB3_UNI_QSERDES_COM_SSC_PER1 (0x0000 + 0x001c)
#define USB3_UNI_QSERDES_COM_SSC_PER2 (0x0000 + 0x0020)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 (0x0000 + 0x0024)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 (0x0000 + 0x0028)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 (0x0000 + 0x002c)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 (0x0000 + 0x0030)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 (0x0000 + 0x0034)
#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 (0x0000 + 0x0038)
#define USB3_UNI_QSERDES_COM_POST_DIV (0x0000 + 0x003c)
#define USB3_UNI_QSERDES_COM_POST_DIV_MUX (0x0000 + 0x0040)
#define USB3_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x0000 + 0x0044)
#define USB3_UNI_QSERDES_COM_CLK_ENABLE1 (0x0000 + 0x0048)
#define USB3_UNI_QSERDES_COM_SYS_CLK_CTRL (0x0000 + 0x004c)
#define USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE (0x0000 + 0x0050)
#define USB3_UNI_QSERDES_COM_PLL_EN (0x0000 + 0x0054)
#define USB3_UNI_QSERDES_COM_PLL_IVCO (0x0000 + 0x0058)
#define USB3_UNI_QSERDES_COM_CMN_IETRIM (0x0000 + 0x005c)
#define USB3_UNI_QSERDES_COM_CMN_IPTRIM (0x0000 + 0x0060)
#define USB3_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL (0x0000 + 0x0064)
#define USB3_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x0000 + 0x0068)
#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 (0x0000 + 0x006c)
#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 (0x0000 + 0x0070)
#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 (0x0000 + 0x0074)
#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 (0x0000 + 0x0078)
#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 (0x0000 + 0x007c)
#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 (0x0000 + 0x0080)
#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 (0x0000 + 0x0084)
#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 (0x0000 + 0x0088)
#define USB3_UNI_QSERDES_COM_PLL_CNTRL (0x0000 + 0x008c)
#define USB3_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM (0x0000 + 0x0090)
#define USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL (0x0000 + 0x0094)
#define USB3_UNI_QSERDES_COM_CML_SYSCLK_SEL (0x0000 + 0x0098)
#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL (0x0000 + 0x009c)
#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL2 (0x0000 + 0x00a0)
#define USB3_UNI_QSERDES_COM_LOCK_CMP_EN (0x0000 + 0x00a4)
#define USB3_UNI_QSERDES_COM_LOCK_CMP_CFG (0x0000 + 0x00a8)
#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 (0x0000 + 0x00ac)
#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 (0x0000 + 0x00b0)
#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 (0x0000 + 0x00b4)
#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 (0x0000 + 0x00b8)
#define USB3_UNI_QSERDES_COM_DEC_START_MODE0 (0x0000 + 0x00bc)
#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE0 (0x0000 + 0x00c0)
#define USB3_UNI_QSERDES_COM_DEC_START_MODE1 (0x0000 + 0x00c4)
#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE1 (0x0000 + 0x00c8)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 (0x0000 + 0x00cc)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 (0x0000 + 0x00d0)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 (0x0000 + 0x00d4)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 (0x0000 + 0x00d8)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 (0x0000 + 0x00dc)
#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 (0x0000 + 0x00e0)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_INITVAL (0x0000 + 0x00e4)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_EN (0x0000 + 0x00e8)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (0x0000 + 0x00ec)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (0x0000 + 0x00f0)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (0x0000 + 0x00f4)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (0x0000 + 0x00f8)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 (0x0000 + 0x00fc)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 (0x0000 + 0x0100)
#define USB3_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL (0x0000 + 0x0104)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_CTRL (0x0000 + 0x0108)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAP (0x0000 + 0x010c)
#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 (0x0000 + 0x0110)
#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE0 (0x0000 + 0x0114)
#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 (0x0000 + 0x0118)
#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 (0x0000 + 0x011c)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 (0x0000 + 0x0120)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 (0x0000 + 0x0124)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 (0x0000 + 0x0128)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 (0x0000 + 0x012c)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 (0x0000 + 0x0130)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 (0x0000 + 0x0134)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER1 (0x0000 + 0x0138)
#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER2 (0x0000 + 0x013c)
#define USB3_UNI_QSERDES_COM_CMN_STATUS (0x0000 + 0x0140)
#define USB3_UNI_QSERDES_COM_RESET_SM_STATUS (0x0000 + 0x0144)
#define USB3_UNI_QSERDES_COM_RESTRIM_CODE_STATUS (0x0000 + 0x0148)
#define USB3_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS (0x0000 + 0x014c)
#define USB3_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS (0x0000 + 0x0150)
#define USB3_UNI_QSERDES_COM_CLK_SELECT (0x0000 + 0x0154)
#define USB3_UNI_QSERDES_COM_HSCLK_SEL (0x0000 + 0x0158)
#define USB3_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL (0x0000 + 0x015c)
#define USB3_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x0000 + 0x0160)
#define USB3_UNI_QSERDES_COM_PLL_ANALOG (0x0000 + 0x0164)
#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE0 (0x0000 + 0x0168)
#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 (0x0000 + 0x016c)
#define USB3_UNI_QSERDES_COM_SW_RESET (0x0000 + 0x0170)
#define USB3_UNI_QSERDES_COM_CORE_CLK_EN (0x0000 + 0x0174)
#define USB3_UNI_QSERDES_COM_C_READY_STATUS (0x0000 + 0x0178)
#define USB3_UNI_QSERDES_COM_CMN_CONFIG (0x0000 + 0x017c)
#define USB3_UNI_QSERDES_COM_CMN_RATE_OVERRIDE (0x0000 + 0x0180)
#define USB3_UNI_QSERDES_COM_SVS_MODE_CLK_SEL (0x0000 + 0x0184)
#define USB3_UNI_QSERDES_COM_DEBUG_BUS0 (0x0000 + 0x0188)
#define USB3_UNI_QSERDES_COM_DEBUG_BUS1 (0x0000 + 0x018c)
#define USB3_UNI_QSERDES_COM_DEBUG_BUS2 (0x0000 + 0x0190)
#define USB3_UNI_QSERDES_COM_DEBUG_BUS3 (0x0000 + 0x0194)
#define USB3_UNI_QSERDES_COM_DEBUG_BUS_SEL (0x0000 + 0x0198)
#define USB3_UNI_QSERDES_COM_CMN_MISC1 (0x0000 + 0x019c)
#define USB3_UNI_QSERDES_COM_CMN_MODE (0x0000 + 0x01a0)
#define USB3_UNI_QSERDES_COM_CMN_MODE_CONTD (0x0000 + 0x01a4)
#define USB3_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL (0x0000 + 0x01a8)
#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (0x0000 + 0x01ac)
#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (0x0000 + 0x01b0)
#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 (0x0000 + 0x01b4)
#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 (0x0000 + 0x01b8)
#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL (0x0000 + 0x01bc)
#define USB3_UNI_QSERDES_COM_RESERVED_1 (0x0000 + 0x01c0)
#define USB3_UNI_QSERDES_COM_MODE_OPERATION_STATUS (0x0000 + 0x01c4)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
#define USB3_UNI_PCS_SW_RESET (0x0200 + 0x0000)
#define USB3_UNI_PCS_REVISION_ID0 (0x0200 + 0x0004)
#define USB3_UNI_PCS_REVISION_ID1 (0x0200 + 0x0008)
#define USB3_UNI_PCS_REVISION_ID2 (0x0200 + 0x000c)
#define USB3_UNI_PCS_REVISION_ID3 (0x0200 + 0x0010)
#define USB3_UNI_PCS_PCS_STATUS1 (0x0200 + 0x0014)
#define USB3_UNI_PCS_PCS_STATUS2 (0x0200 + 0x0018)
#define USB3_UNI_PCS_PCS_STATUS3 (0x0200 + 0x001c)
#define USB3_UNI_PCS_PCS_STATUS4 (0x0200 + 0x0020)
#define USB3_UNI_PCS_PCS_STATUS5 (0x0200 + 0x0024)
#define USB3_UNI_PCS_PCS_STATUS6 (0x0200 + 0x0028)
#define USB3_UNI_PCS_PCS_STATUS7 (0x0200 + 0x002c)
#define USB3_UNI_PCS_DEBUG_BUS_0_STATUS (0x0200 + 0x0030)
#define USB3_UNI_PCS_DEBUG_BUS_1_STATUS (0x0200 + 0x0034)
#define USB3_UNI_PCS_DEBUG_BUS_2_STATUS (0x0200 + 0x0038)
#define USB3_UNI_PCS_DEBUG_BUS_3_STATUS (0x0200 + 0x003c)
#define USB3_UNI_PCS_POWER_DOWN_CONTROL (0x0200 + 0x0040)
#define USB3_UNI_PCS_START_CONTROL (0x0200 + 0x0044)
#define USB3_UNI_PCS_INSIG_SW_CTRL1 (0x0200 + 0x0048)
#define USB3_UNI_PCS_INSIG_SW_CTRL2 (0x0200 + 0x004c)
#define USB3_UNI_PCS_INSIG_SW_CTRL3 (0x0200 + 0x0050)
#define USB3_UNI_PCS_INSIG_SW_CTRL4 (0x0200 + 0x0054)
#define USB3_UNI_PCS_INSIG_SW_CTRL5 (0x0200 + 0x0058)
#define USB3_UNI_PCS_INSIG_SW_CTRL6 (0x0200 + 0x005c)
#define USB3_UNI_PCS_INSIG_SW_CTRL7 (0x0200 + 0x0060)
#define USB3_UNI_PCS_INSIG_SW_CTRL8 (0x0200 + 0x0064)
#define USB3_UNI_PCS_INSIG_MX_CTRL1 (0x0200 + 0x0068)
#define USB3_UNI_PCS_INSIG_MX_CTRL2 (0x0200 + 0x006c)
#define USB3_UNI_PCS_INSIG_MX_CTRL3 (0x0200 + 0x0070)
#define USB3_UNI_PCS_INSIG_MX_CTRL4 (0x0200 + 0x0074)
#define USB3_UNI_PCS_INSIG_MX_CTRL5 (0x0200 + 0x0078)
#define USB3_UNI_PCS_INSIG_MX_CTRL7 (0x0200 + 0x007c)
#define USB3_UNI_PCS_INSIG_MX_CTRL8 (0x0200 + 0x0080)
#define USB3_UNI_PCS_OUTSIG_SW_CTRL1 (0x0200 + 0x0084)
#define USB3_UNI_PCS_OUTSIG_MX_CTRL1 (0x0200 + 0x0088)
#define USB3_UNI_PCS_CLAMP_ENABLE (0x0200 + 0x008c)
#define USB3_UNI_PCS_POWER_STATE_CONFIG1 (0x0200 + 0x0090)
#define USB3_UNI_PCS_POWER_STATE_CONFIG2 (0x0200 + 0x0094)
#define USB3_UNI_PCS_FLL_CNTRL1 (0x0200 + 0x0098)
#define USB3_UNI_PCS_FLL_CNTRL2 (0x0200 + 0x009c)
#define USB3_UNI_PCS_FLL_CNT_VAL_L (0x0200 + 0x00a0)
#define USB3_UNI_PCS_FLL_CNT_VAL_H_TOL (0x0200 + 0x00a4)
#define USB3_UNI_PCS_FLL_MAN_CODE (0x0200 + 0x00a8)
#define USB3_UNI_PCS_TEST_CONTROL1 (0x0200 + 0x00ac)
#define USB3_UNI_PCS_TEST_CONTROL2 (0x0200 + 0x00b0)
#define USB3_UNI_PCS_TEST_CONTROL3 (0x0200 + 0x00b4)
#define USB3_UNI_PCS_TEST_CONTROL4 (0x0200 + 0x00b8)
#define USB3_UNI_PCS_TEST_CONTROL5 (0x0200 + 0x00bc)
#define USB3_UNI_PCS_TEST_CONTROL6 (0x0200 + 0x00c0)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG1 (0x0200 + 0x00c4)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG2 (0x0200 + 0x00c8)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG3 (0x0200 + 0x00cc)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG4 (0x0200 + 0x00d0)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG5 (0x0200 + 0x00d4)
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG6 (0x0200 + 0x00d8)
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG1 (0x0200 + 0x00dc)
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG2 (0x0200 + 0x00e0)
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG3 (0x0200 + 0x00e4)
#define USB3_UNI_PCS_BIST_CTRL (0x0200 + 0x00e8)
#define USB3_UNI_PCS_PRBS_POLY0 (0x0200 + 0x00ec)
#define USB3_UNI_PCS_PRBS_POLY1 (0x0200 + 0x00f0)
#define USB3_UNI_PCS_FIXED_PAT0 (0x0200 + 0x00f4)
#define USB3_UNI_PCS_FIXED_PAT1 (0x0200 + 0x00f8)
#define USB3_UNI_PCS_FIXED_PAT2 (0x0200 + 0x00fc)
#define USB3_UNI_PCS_FIXED_PAT3 (0x0200 + 0x0100)
#define USB3_UNI_PCS_FIXED_PAT4 (0x0200 + 0x0104)
#define USB3_UNI_PCS_FIXED_PAT5 (0x0200 + 0x0108)
#define USB3_UNI_PCS_FIXED_PAT6 (0x0200 + 0x010c)
#define USB3_UNI_PCS_FIXED_PAT7 (0x0200 + 0x0110)
#define USB3_UNI_PCS_FIXED_PAT8 (0x0200 + 0x0114)
#define USB3_UNI_PCS_FIXED_PAT9 (0x0200 + 0x0118)
#define USB3_UNI_PCS_FIXED_PAT10 (0x0200 + 0x011c)
#define USB3_UNI_PCS_FIXED_PAT11 (0x0200 + 0x0120)
#define USB3_UNI_PCS_FIXED_PAT12 (0x0200 + 0x0124)
#define USB3_UNI_PCS_FIXED_PAT13 (0x0200 + 0x0128)
#define USB3_UNI_PCS_FIXED_PAT14 (0x0200 + 0x012c)
#define USB3_UNI_PCS_FIXED_PAT15 (0x0200 + 0x0130)
#define USB3_UNI_PCS_TXMGN_CONFIG (0x0200 + 0x0134)
#define USB3_UNI_PCS_G12S1_TXMGN_V0 (0x0200 + 0x0138)
#define USB3_UNI_PCS_G12S1_TXMGN_V1 (0x0200 + 0x013c)
#define USB3_UNI_PCS_G12S1_TXMGN_V2 (0x0200 + 0x0140)
#define USB3_UNI_PCS_G12S1_TXMGN_V3 (0x0200 + 0x0144)
#define USB3_UNI_PCS_G12S1_TXMGN_V4 (0x0200 + 0x0148)
#define USB3_UNI_PCS_G12S1_TXMGN_V0_RS (0x0200 + 0x014c)
#define USB3_UNI_PCS_G12S1_TXMGN_V1_RS (0x0200 + 0x0150)
#define USB3_UNI_PCS_G12S1_TXMGN_V2_RS (0x0200 + 0x0154)
#define USB3_UNI_PCS_G12S1_TXMGN_V3_RS (0x0200 + 0x0158)
#define USB3_UNI_PCS_G12S1_TXMGN_V4_RS (0x0200 + 0x015c)
#define USB3_UNI_PCS_G3S2_TXMGN_MAIN (0x0200 + 0x0160)
#define USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS (0x0200 + 0x0164)
#define USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB (0x0200 + 0x0168)
#define USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB (0x0200 + 0x016c)
#define USB3_UNI_PCS_G3S2_PRE_GAIN (0x0200 + 0x0170)
#define USB3_UNI_PCS_G3S2_POST_GAIN (0x0200 + 0x0174)
#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET (0x0200 + 0x0178)
#define USB3_UNI_PCS_G3S2_PRE_GAIN_RS (0x0200 + 0x017c)
#define USB3_UNI_PCS_G3S2_POST_GAIN_RS (0x0200 + 0x0180)
#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS (0x0200 + 0x0184)
#define USB3_UNI_PCS_RX_SIGDET_LVL (0x0200 + 0x0188)
#define USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL (0x0200 + 0x018c)
#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L (0x0200 + 0x0190)
#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H (0x0200 + 0x0194)
#define USB3_UNI_PCS_RATE_SLEW_CNTRL1 (0x0200 + 0x0198)
#define USB3_UNI_PCS_RATE_SLEW_CNTRL2 (0x0200 + 0x019c)
#define USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK (0x0200 + 0x01a0)
#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L (0x0200 + 0x01a4)
#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H (0x0200 + 0x01a8)
#define USB3_UNI_PCS_TSYNC_RSYNC_TIME (0x0200 + 0x01ac)
#define USB3_UNI_PCS_CDR_RESET_TIME (0x0200 + 0x01b0)
#define USB3_UNI_PCS_TSYNC_DLY_TIME (0x0200 + 0x01b4)
#define USB3_UNI_PCS_ELECIDLE_DLY_SEL (0x0200 + 0x01b8)
#define USB3_UNI_PCS_CMN_ACK_OUT_SEL (0x0200 + 0x01bc)
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 (0x0200 + 0x01c0)
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 (0x0200 + 0x01c4)
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 (0x0200 + 0x01c8)
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 (0x0200 + 0x01cc)
#define USB3_UNI_PCS_PCS_TX_RX_CONFIG (0x0200 + 0x01d0)
#define USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL (0x0200 + 0x01d4)
#define USB3_UNI_PCS_RX_DCC_CAL_CONFIG (0x0200 + 0x01d8)
#define USB3_UNI_PCS_EQ_CONFIG1 (0x0200 + 0x01dc)
#define USB3_UNI_PCS_EQ_CONFIG2 (0x0200 + 0x01e0)
#define USB3_UNI_PCS_EQ_CONFIG3 (0x0200 + 0x01e4)
#define USB3_UNI_PCS_EQ_CONFIG4 (0x0200 + 0x01e8)
#define USB3_UNI_PCS_EQ_CONFIG5 (0x0200 + 0x01ec)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE */
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS (0x0600 + 0x0000)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS (0x0600 + 0x0004)
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 (0x0600 + 0x0008)
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 (0x0600 + 0x000c)
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 (0x0600 + 0x0010)
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 (0x0600 + 0x0014)
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG5 (0x0600 + 0x0018)
#define USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG (0x0600 + 0x001c)
#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE (0x0600 + 0x0020)
#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL (0x0600 + 0x0024)
#define USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK (0x0600 + 0x0028)
#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L (0x0600 + 0x002c)
#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H (0x0600 + 0x0030)
#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 (0x0600 + 0x0034)
#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 (0x0600 + 0x0038)
#define USB3_UNI_PCS_PCIE_SIGDET_CNTRL (0x0600 + 0x003c)
#define USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME (0x0600 + 0x0040)
#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L (0x0600 + 0x0044)
#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H (0x0600 + 0x0048)
#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L (0x0600 + 0x004c)
#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H (0x0600 + 0x0050)
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 (0x0600 + 0x0054)
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 (0x0600 + 0x0058)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 (0x0600 + 0x005c)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 (0x0600 + 0x0060)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 (0x0600 + 0x0064)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 (0x0600 + 0x0068)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 (0x0600 + 0x006c)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 (0x0600 + 0x0070)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 (0x0600 + 0x0074)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 (0x0600 + 0x0078)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 (0x0600 + 0x007c)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 (0x0600 + 0x0080)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 (0x0600 + 0x0084)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 (0x0600 + 0x0088)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 (0x0600 + 0x008c)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 (0x0600 + 0x0090)
#define USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS (0x0600 + 0x0094)
#define USB3_UNI_PCS_PCIE_LOCAL_FS (0x0600 + 0x0098)
#define USB3_UNI_PCS_PCIE_LOCAL_LF (0x0600 + 0x009c)
#define USB3_UNI_PCS_PCIE_LOCAL_FS_RS (0x0600 + 0x00a0)
#define USB3_UNI_PCS_PCIE_EQ_CONFIG1 (0x0600 + 0x00a4)
#define USB3_UNI_PCS_PCIE_EQ_CONFIG2 (0x0600 + 0x00a8)
#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE (0x0600 + 0x00ac)
#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE (0x0600 + 0x00b0)
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE (0x0600 + 0x00b4)
#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE (0x0600 + 0x00b8)
#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE (0x0600 + 0x00bc)
#define USB3_UNI_PCS_PCIE_PRESET_P10_PRE (0x0600 + 0x00c0)
#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS (0x0600 + 0x00c4)
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS (0x0600 + 0x00c8)
#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS (0x0600 + 0x00cc)
#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST (0x0600 + 0x00d0)
#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST (0x0600 + 0x00d4)
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST (0x0600 + 0x00d8)
#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST (0x0600 + 0x00dc)
#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST (0x0600 + 0x00e0)
#define USB3_UNI_PCS_PCIE_PRESET_P10_POST (0x0600 + 0x00e4)
#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS (0x0600 + 0x00e8)
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS (0x0600 + 0x00ec)
#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS (0x0600 + 0x00f0)
#define USB3_UNI_PCS_PCIE_RXEQEVAL_TIME (0x0600 + 0x00f4)
/* Module:
* USB3_UNI_PHY_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_DEBUG_INTGEN
*/
#define USB3_UNI_PCS_INTGEN_INTGEN_STATUS1 (0x0800 + 0x0000)
#define USB3_UNI_PCS_INTGEN_INTGEN_STATUS2 (0x0800 + 0x0004)
#define USB3_UNI_PCS_INTGEN_CONFIG1 (0x0800 + 0x0008)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1 (0x0800 + 0x000c)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2 (0x0800 + 0x0010)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3 (0x0800 + 0x0014)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4 (0x0800 + 0x0018)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5 (0x0800 + 0x001c)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1 (0x0800 + 0x0020)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2 (0x0800 + 0x0024)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3 (0x0800 + 0x0028)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4 (0x0800 + 0x002c)
#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5 (0x0800 + 0x0030)
#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1 (0x0800 + 0x0034)
#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2 (0x0800 + 0x0038)
#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3 (0x0800 + 0x003c)
#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4 (0x0800 + 0x0040)
#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5 (0x0800 + 0x0044)
#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1 (0x0800 + 0x0048)
#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2 (0x0800 + 0x004c)
#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3 (0x0800 + 0x0050)
#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4 (0x0800 + 0x0054)
#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5 (0x0800 + 0x0058)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
#define USB3_UNI_PCS_LN_PCS_STATUS1 (0x0a00 + 0x0000)
#define USB3_UNI_PCS_LN_PCS_STATUS2 (0x0a00 + 0x0004)
#define USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR (0x0a00 + 0x0008)
#define USB3_UNI_PCS_LN_PCS_STATUS3 (0x0a00 + 0x000c)
#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS (0x0a00 + 0x0010)
#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS (0x0a00 + 0x0014)
#define USB3_UNI_PCS_LN_BIST_CHK_STATUS (0x0a00 + 0x0018)
#define USB3_UNI_PCS_LN_INSIG_SW_CTRL1 (0x0a00 + 0x001c)
#define USB3_UNI_PCS_LN_INSIG_MX_CTRL1 (0x0a00 + 0x0020)
#define USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 (0x0a00 + 0x0024)
#define USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 (0x0a00 + 0x0028)
#define USB3_UNI_PCS_LN_TEST_CONTROL1 (0x0a00 + 0x002c)
#define USB3_UNI_PCS_LN_BIST_CTRL (0x0a00 + 0x0030)
#define USB3_UNI_PCS_LN_PRBS_SEED0 (0x0a00 + 0x0034)
#define USB3_UNI_PCS_LN_PRBS_SEED1 (0x0a00 + 0x0038)
#define USB3_UNI_PCS_LN_FIXED_PAT_CTRL (0x0a00 + 0x003c)
#define USB3_UNI_PCS_LN_EQ_CONFIG (0x0a00 + 0x0040)
#define USB3_UNI_PCS_LN_TEST_CONTROL2 (0x0a00 + 0x0044)
#define USB3_UNI_PCS_LN_TEST_CONTROL3 (0x0a00 + 0x0048)
/* Module:
* USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE
*/
#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST (0x0c00 + 0x0000)
#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS (0x0c00 + 0x0004)
#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN (0x0c00 + 0x0008)
#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_L (0x0c00 + 0x000c)
#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_H (0x0c00 + 0x0010)
#define USB3_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG (0x0c00 + 0x0014)
#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 (0x0c00 + 0x0018)
#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 (0x0c00 + 0x001c)
#define USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS (0x0c00 + 0x0020)
#define USB3_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2 (0x0c00 + 0x0024)
#define USB3_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2 (0x0c00 + 0x0028)
/* Module: USB3_UNI_PHY_QSERDES_TX_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
#define USB3_UNI_QSERDES_TX_BIST_MODE_LANENO (0x0e00 + 0x0000)
#define USB3_UNI_QSERDES_TX_BIST_INVERT (0x0e00 + 0x0004)
#define USB3_UNI_QSERDES_TX_CLKBUF_ENABLE (0x0e00 + 0x0008)
#define USB3_UNI_QSERDES_TX_TX_EMP_POST1_LVL (0x0e00 + 0x000c)
#define USB3_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP (0x0e00 + 0x0010)
#define USB3_UNI_QSERDES_TX_TX_DRV_LVL (0x0e00 + 0x0014)
#define USB3_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET (0x0e00 + 0x0018)
#define USB3_UNI_QSERDES_TX_RESET_TSYNC_EN (0x0e00 + 0x001c)
#define USB3_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN (0x0e00 + 0x0020)
#define USB3_UNI_QSERDES_TX_TX_BAND (0x0e00 + 0x0024)
#define USB3_UNI_QSERDES_TX_SLEW_CNTL (0x0e00 + 0x0028)
#define USB3_UNI_QSERDES_TX_INTERFACE_SELECT (0x0e00 + 0x002c)
#define USB3_UNI_QSERDES_TX_LPB_EN (0x0e00 + 0x0030)
#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX (0x0e00 + 0x0034)
#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX (0x0e00 + 0x0038)
#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX (0x0e00 + 0x003c)
#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX (0x0e00 + 0x0040)
#define USB3_UNI_QSERDES_TX_PERL_LENGTH1 (0x0e00 + 0x0044)
#define USB3_UNI_QSERDES_TX_PERL_LENGTH2 (0x0e00 + 0x0048)
#define USB3_UNI_QSERDES_TX_SERDES_BYP_EN_OUT (0x0e00 + 0x004c)
#define USB3_UNI_QSERDES_TX_DEBUG_BUS_SEL (0x0e00 + 0x0050)
#define USB3_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN (0x0e00 + 0x0054)
#define USB3_UNI_QSERDES_TX_HIGHZ_DRVR_EN (0x0e00 + 0x0058)
#define USB3_UNI_QSERDES_TX_TX_POL_INV (0x0e00 + 0x005c)
#define USB3_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN (0x0e00 + 0x0060)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN1 (0x0e00 + 0x0064)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN2 (0x0e00 + 0x0068)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN3 (0x0e00 + 0x006c)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN4 (0x0e00 + 0x0070)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN5 (0x0e00 + 0x0074)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN6 (0x0e00 + 0x0078)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN7 (0x0e00 + 0x007c)
#define USB3_UNI_QSERDES_TX_BIST_PATTERN8 (0x0e00 + 0x0080)
#define USB3_UNI_QSERDES_TX_LANE_MODE_1 (0x0e00 + 0x0084)
#define USB3_UNI_QSERDES_TX_LANE_MODE_2 (0x0e00 + 0x0088)
#define USB3_UNI_QSERDES_TX_LANE_MODE_3 (0x0e00 + 0x008c)
#define USB3_UNI_QSERDES_TX_LANE_MODE_4 (0x0e00 + 0x0090)
#define USB3_UNI_QSERDES_TX_LANE_MODE_5 (0x0e00 + 0x0094)
#define USB3_UNI_QSERDES_TX_ATB_SEL1 (0x0e00 + 0x0098)
#define USB3_UNI_QSERDES_TX_ATB_SEL2 (0x0e00 + 0x009c)
#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL (0x0e00 + 0x00a0)
#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 (0x0e00 + 0x00a4)
#define USB3_UNI_QSERDES_TX_PRBS_SEED1 (0x0e00 + 0x00a8)
#define USB3_UNI_QSERDES_TX_PRBS_SEED2 (0x0e00 + 0x00ac)
#define USB3_UNI_QSERDES_TX_PRBS_SEED3 (0x0e00 + 0x00b0)
#define USB3_UNI_QSERDES_TX_PRBS_SEED4 (0x0e00 + 0x00b4)
#define USB3_UNI_QSERDES_TX_RESET_GEN (0x0e00 + 0x00b8)
#define USB3_UNI_QSERDES_TX_RESET_GEN_MUXES (0x0e00 + 0x00bc)
#define USB3_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN (0x0e00 + 0x00c0)
#define USB3_UNI_QSERDES_TX_TX_INTERFACE_MODE (0x0e00 + 0x00c4)
#define USB3_UNI_QSERDES_TX_VMODE_CTRL1 (0x0e00 + 0x00c8)
#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 (0x0e00 + 0x00cc)
#define USB3_UNI_QSERDES_TX_BIST_STATUS (0x0e00 + 0x00d0)
#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT1 (0x0e00 + 0x00d4)
#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT2 (0x0e00 + 0x00d8)
#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 (0x0e00 + 0x00dc)
#define USB3_UNI_QSERDES_TX_LANE_DIG_CONFIG (0x0e00 + 0x00e0)
#define USB3_UNI_QSERDES_TX_PI_QEC_CTRL (0x0e00 + 0x00e4)
#define USB3_UNI_QSERDES_TX_PRE_EMPH (0x0e00 + 0x00e8)
#define USB3_UNI_QSERDES_TX_SW_RESET (0x0e00 + 0x00ec)
#define USB3_UNI_QSERDES_TX_DCC_OFFSET (0x0e00 + 0x00f0)
#define USB3_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET (0x0e00 + 0x00f4)
#define USB3_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1 (0x0e00 + 0x00f8)
#define USB3_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2 (0x0e00 + 0x00fc)
#define USB3_UNI_QSERDES_TX_DIG_BKUP_CTRL (0x0e00 + 0x0100)
#define USB3_UNI_QSERDES_TX_DEBUG_BUS0 (0x0e00 + 0x0104)
#define USB3_UNI_QSERDES_TX_DEBUG_BUS1 (0x0e00 + 0x0108)
#define USB3_UNI_QSERDES_TX_DEBUG_BUS2 (0x0e00 + 0x010c)
#define USB3_UNI_QSERDES_TX_DEBUG_BUS3 (0x0e00 + 0x0110)
#define USB3_UNI_QSERDES_TX_READ_EQCODE (0x0e00 + 0x0114)
#define USB3_UNI_QSERDES_TX_READ_OFFSETCODE (0x0e00 + 0x0118)
#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW (0x0e00 + 0x011c)
#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH (0x0e00 + 0x0120)
#define USB3_UNI_QSERDES_TX_VGA_READ_CODE (0x0e00 + 0x0124)
#define USB3_UNI_QSERDES_TX_VTH_READ_CODE (0x0e00 + 0x0128)
#define USB3_UNI_QSERDES_TX_DFE_TAP1_READ_CODE (0x0e00 + 0x012c)
#define USB3_UNI_QSERDES_TX_DFE_TAP2_READ_CODE (0x0e00 + 0x0130)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_I (0x0e00 + 0x0134)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_IBAR (0x0e00 + 0x0138)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_Q (0x0e00 + 0x013c)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_QBAR (0x0e00 + 0x0140)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_A (0x0e00 + 0x0144)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_ABAR (0x0e00 + 0x0148)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SM_ON (0x0e00 + 0x014c)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE (0x0e00 + 0x0150)
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR (0x0e00 + 0x0154)
#define USB3_UNI_QSERDES_TX_DCC_CAL_STATUS (0x0e00 + 0x0158)
#define USB3_UNI_QSERDES_TX_DCC_READ_CODE_STATUS (0x0e00 + 0x015c)
/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF (0x1000 + 0x0000)
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER (0x1000 + 0x0004)
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN (0x1000 + 0x0008)
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF (0x1000 + 0x000c)
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER (0x1000 + 0x0010)
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN (0x1000 + 0x0014)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF (0x1000 + 0x0018)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER (0x1000 + 0x001c)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN (0x1000 + 0x0020)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF (0x1000 + 0x0024)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER (0x1000 + 0x0028)
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN (0x1000 + 0x002c)
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (0x1000 + 0x0030)
#define USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (0x1000 + 0x0034)
#define USB3_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY (0x1000 + 0x0038)
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (0x1000 + 0x003c)
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (0x1000 + 0x0040)
#define USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS (0x1000 + 0x0044)
#define USB3_UNI_QSERDES_RX_UCDR_PI_CTRL2 (0x1000 + 0x0048)
#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 (0x1000 + 0x004c)
#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 (0x1000 + 0x0050)
#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 (0x1000 + 0x0054)
#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 (0x1000 + 0x0058)
#define USB3_UNI_QSERDES_RX_AUX_CONTROL (0x1000 + 0x005c)
#define USB3_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE (0x1000 + 0x0060)
#define USB3_UNI_QSERDES_RX_RCLK_AUXDATA_SEL (0x1000 + 0x0064)
#define USB3_UNI_QSERDES_RX_AC_JTAG_ENABLE (0x1000 + 0x0068)
#define USB3_UNI_QSERDES_RX_AC_JTAG_INITP (0x1000 + 0x006c)
#define USB3_UNI_QSERDES_RX_AC_JTAG_INITN (0x1000 + 0x0070)
#define USB3_UNI_QSERDES_RX_AC_JTAG_LVL (0x1000 + 0x0074)
#define USB3_UNI_QSERDES_RX_AC_JTAG_MODE (0x1000 + 0x0078)
#define USB3_UNI_QSERDES_RX_AC_JTAG_RESET (0x1000 + 0x007c)
#define USB3_UNI_QSERDES_RX_RX_TERM_BW (0x1000 + 0x0080)
#define USB3_UNI_QSERDES_RX_RX_RCVR_IQ_EN (0x1000 + 0x0084)
#define USB3_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS (0x1000 + 0x0088)
#define USB3_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS (0x1000 + 0x008c)
#define USB3_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS (0x1000 + 0x0090)
#define USB3_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS (0x1000 + 0x0094)
#define USB3_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS (0x1000 + 0x0098)
#define USB3_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS (0x1000 + 0x009c)
#define USB3_UNI_QSERDES_RX_RX_IDAC_EN (0x1000 + 0x00a0)
#define USB3_UNI_QSERDES_RX_RX_IDAC_ENABLES (0x1000 + 0x00a4)
#define USB3_UNI_QSERDES_RX_RX_IDAC_SIGN (0x1000 + 0x00a8)
#define USB3_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE (0x1000 + 0x00ac)
#define USB3_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x1000 + 0x00b0)
#define USB3_UNI_QSERDES_RX_DFE_1 (0x1000 + 0x00b4)
#define USB3_UNI_QSERDES_RX_DFE_2 (0x1000 + 0x00b8)
#define USB3_UNI_QSERDES_RX_DFE_3 (0x1000 + 0x00bc)
#define USB3_UNI_QSERDES_RX_DFE_4 (0x1000 + 0x00c0)
#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 (0x1000 + 0x00c4)
#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 (0x1000 + 0x00c8)
#define USB3_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH (0x1000 + 0x00cc)
#define USB3_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH (0x1000 + 0x00d0)
#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 (0x1000 + 0x00d4)
#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 (0x1000 + 0x00d8)
#define USB3_UNI_QSERDES_RX_GM_CAL (0x1000 + 0x00dc)
#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB (0x1000 + 0x00e0)
#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB (0x1000 + 0x00e4)
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (0x1000 + 0x00e8)
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (0x1000 + 0x00ec)
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (0x1000 + 0x00f0)
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (0x1000 + 0x00f4)
#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW (0x1000 + 0x00f8)
#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH (0x1000 + 0x00fc)
#define USB3_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME (0x1000 + 0x0100)
#define USB3_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR (0x1000 + 0x0104)
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB (0x1000 + 0x0108)
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB (0x1000 + 0x010c)
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x1000 + 0x0110)
#define USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (0x1000 + 0x0114)
#define USB3_UNI_QSERDES_RX_SIGDET_ENABLES (0x1000 + 0x0118)
#define USB3_UNI_QSERDES_RX_SIGDET_CNTRL (0x1000 + 0x011c)
#define USB3_UNI_QSERDES_RX_SIGDET_LVL (0x1000 + 0x0120)
#define USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL (0x1000 + 0x0124)
#define USB3_UNI_QSERDES_RX_RX_BAND (0x1000 + 0x0128)
#define USB3_UNI_QSERDES_RX_CDR_FREEZE_UP_DN (0x1000 + 0x012c)
#define USB3_UNI_QSERDES_RX_CDR_RESET_OVERRIDE (0x1000 + 0x0130)
#define USB3_UNI_QSERDES_RX_RX_INTERFACE_MODE (0x1000 + 0x0134)
#define USB3_UNI_QSERDES_RX_JITTER_GEN_MODE (0x1000 + 0x0138)
#define USB3_UNI_QSERDES_RX_SJ_AMP1 (0x1000 + 0x013c)
#define USB3_UNI_QSERDES_RX_SJ_AMP2 (0x1000 + 0x0140)
#define USB3_UNI_QSERDES_RX_SJ_PER1 (0x1000 + 0x0144)
#define USB3_UNI_QSERDES_RX_SJ_PER2 (0x1000 + 0x0148)
#define USB3_UNI_QSERDES_RX_PPM_OFFSET1 (0x1000 + 0x014c)
#define USB3_UNI_QSERDES_RX_PPM_OFFSET2 (0x1000 + 0x0150)
#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 (0x1000 + 0x0154)
#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 (0x1000 + 0x0158)
#define USB3_UNI_QSERDES_RX_RX_MODE_00_LOW (0x1000 + 0x015c)
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH (0x1000 + 0x0160)
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 (0x1000 + 0x0164)
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 (0x1000 + 0x0168)
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 (0x1000 + 0x016c)
#define USB3_UNI_QSERDES_RX_RX_MODE_01_LOW (0x1000 + 0x0170)
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH (0x1000 + 0x0174)
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 (0x1000 + 0x0178)
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 (0x1000 + 0x017c)
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 (0x1000 + 0x0180)
#define USB3_UNI_QSERDES_RX_RX_MODE_10_LOW (0x1000 + 0x0184)
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH (0x1000 + 0x0188)
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH2 (0x1000 + 0x018c)
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH3 (0x1000 + 0x0190)
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH4 (0x1000 + 0x0194)
#define USB3_UNI_QSERDES_RX_PHPRE_CTRL (0x1000 + 0x0198)
#define USB3_UNI_QSERDES_RX_PHPRE_INITVAL (0x1000 + 0x019c)
#define USB3_UNI_QSERDES_RX_DFE_EN_TIMER (0x1000 + 0x01a0)
#define USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET (0x1000 + 0x01a4)
#define USB3_UNI_QSERDES_RX_DCC_CTRL1 (0x1000 + 0x01a8)
#define USB3_UNI_QSERDES_RX_DCC_CTRL2 (0x1000 + 0x01ac)
#define USB3_UNI_QSERDES_RX_VTH_CODE (0x1000 + 0x01b0)
#define USB3_UNI_QSERDES_RX_VTH_MIN_THRESH (0x1000 + 0x01b4)
#define USB3_UNI_QSERDES_RX_VTH_MAX_THRESH (0x1000 + 0x01b8)
#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 (0x1000 + 0x01bc)
#define USB3_UNI_QSERDES_RX_PI_CTRL1 (0x1000 + 0x01c0)
#define USB3_UNI_QSERDES_RX_PI_CTRL2 (0x1000 + 0x01c4)
#define USB3_UNI_QSERDES_RX_PI_QUAD (0x1000 + 0x01c8)
#define USB3_UNI_QSERDES_RX_IDATA1 (0x1000 + 0x01cc)
#define USB3_UNI_QSERDES_RX_IDATA2 (0x1000 + 0x01d0)
#define USB3_UNI_QSERDES_RX_AUX_DATA1 (0x1000 + 0x01d4)
#define USB3_UNI_QSERDES_RX_AUX_DATA2 (0x1000 + 0x01d8)
#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTP (0x1000 + 0x01dc)
#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTN (0x1000 + 0x01e0)
#define USB3_UNI_QSERDES_RX_RX_SIGDET (0x1000 + 0x01e4)
#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 (0x1000 + 0x01e8)
/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
#define USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 (0x1200 + 0x0000)
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS (0x1200 + 0x0004)
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL (0x1200 + 0x0008)
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 (0x1200 + 0x000c)
#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS (0x1200 + 0x0010)
#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR (0x1200 + 0x0014)
#define USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL (0x1200 + 0x0018)
#define USB3_UNI_PCS_USB3_LFPS_TX_ECSTART (0x1200 + 0x001c)
#define USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL (0x1200 + 0x0020)
#define USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START (0x1200 + 0x0024)
#define USB3_UNI_PCS_USB3_LFPS_CONFIG1 (0x1200 + 0x0028)
#define USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME (0x1200 + 0x002c)
#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME (0x1200 + 0x0030)
#define USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME (0x1200 + 0x0034)
#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 (0x1200 + 0x0038)
#define USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 (0x1200 + 0x003c)
#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L (0x1200 + 0x0040)
#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H (0x1200 + 0x0044)
#define USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD (0x1200 + 0x0048)
#define USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY (0x1200 + 0x004c)
#define USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH (0x1200 + 0x0050)
#define USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL (0x1200 + 0x0054)
#define USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL (0x1200 + 0x0058)
#define USB3_UNI_PCS_USB3_TEST_CONTROL (0x1200 + 0x005c)
#define USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL (0x1200 + 0x0060)
#endif /* _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H */

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include/dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h Normal file
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