ARM: dts: am57xx-beagle-x15: Add support for rev C
Latest update to the BeagleBoard-X15 platform (revision C). This board contains a silicon update (Rev 2.0), which includes a fix for the 2nd ethernet phy when running at 1000 Mbps speeds. This board can be indentified by the [C.00] after [BBRDX15_] in the at24 eeprom: [BBRDX15_C.001731PX150249] Rev C is now in full production and boards are available for end users. https://beagleboard.org/x15 https://github.com/beagleboard/beagleboard-x15/ Signed-off-by: Robert Nelson <robertcnelson@gmail.com> CC: Tony Lindgren <tony@atomide.com> CC: Nishanth Menon <nm@ti.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Jason Kridner <jkridner@beagleboard.org> CC: Drew Fustini <drew@beagleboard.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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committed by
Tony Lindgren
parent
14fc33209a
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c5c3a468e7
@ -651,6 +651,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \
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dtb-$(CONFIG_SOC_DRA7XX) += \
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am57xx-beagle-x15.dtb \
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am57xx-beagle-x15-revb1.dtb \
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am57xx-beagle-x15-revc.dtb \
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am57xx-cl-som-am57x.dtb \
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am57xx-sbc-am57x.dtb \
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am572x-idk.dtb \
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39
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
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39
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
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@ -0,0 +1,39 @@
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/*
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* Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "am57xx-beagle-x15-common.dtsi"
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/ {
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model = "TI AM5728 BeagleBoard-X15 rev C";
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};
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&tpd12s015 {
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gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
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<&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
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<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
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};
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&mmc1 {
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pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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pinctrl-0 = <&mmc1_pins_default>;
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pinctrl-1 = <&mmc1_pins_hs>;
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pinctrl-2 = <&mmc1_pins_sdr12>;
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pinctrl-3 = <&mmc1_pins_sdr25>;
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pinctrl-4 = <&mmc1_pins_sdr50>;
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pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
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pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
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vmmc-supply = <&vdd_3v3>;
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vqmmc-supply = <&ldo1_reg>;
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};
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&mmc2 {
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pinctrl-names = "default", "hs", "ddr_1_8v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_rev20>;
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};
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