Merge "soc: qcom: Fix offset values for non HWKM targets"
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commit
b679be6f20
@ -2,7 +2,7 @@
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/*
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* Common crypto library for storage encryption.
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*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/crypto-qti-common.h>
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@ -188,14 +188,32 @@ static void ice_dump_test_bus(void __iomem *ice_mmio)
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static void ice_dump_config_regs(void __iomem *ice_mmio)
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{
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int i = 0;
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uint32_t version = 0;
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uint32_t major = 0;
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uint32_t minor = 0;
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for (i = 0; i < 64; i++) {
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pr_err("ICE_CRYPTOCFG_r_16 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_CRYPTOCFG_R_16 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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pr_err("ICE_CRYPTOCFG_r_17 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_CRYPTOCFG_R_17 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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version = ice_readl(ice_mmio, ICE_REGS_VERSION);
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major = (version & ICE_CORE_MAJOR_REV_MASK) >> ICE_CORE_MAJOR_REV;
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minor = (version & ICE_CORE_MINOR_REV_MASK) >> ICE_CORE_MINOR_REV;
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if (((major == 3) && (minor >= 2)) || (major > 3)) {
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for (i = 0; i < 64; i++) {
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pr_err("ICE_CRYPTOCFG_r_16 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_CRYPTOCFG_R_16 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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pr_err("ICE_CRYPTOCFG_r_17 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_CRYPTOCFG_R_17 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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}
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} else {
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for (i = 0; i < 32; i++) {
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pr_err("ICE_CRYPTOCFG_r_16 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_SW_CRYPTOCFG_R_16 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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pr_err("ICE_CRYPTOCFG_r_17 slot %d: 0x%08x\n", i,
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ice_readl(ice_mmio, ICE_LUT_KEYS_SW_CRYPTOCFG_R_17 +
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ICE_LUT_KEYS_CRYPTOCFG_OFFSET*i));
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}
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}
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}
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_
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@ -135,13 +135,21 @@
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#define ICE_LUT_KEYS_CRYPTOCFG_R_16 0x4040
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#define ICE_LUT_KEYS_CRYPTOCFG_R_17 0x4044
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#define ICE_LUT_KEYS_CRYPTOCFG_OFFSET 0x80
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_STTS 0x6200
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_MASK 0x6204
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_CLR 0x6208
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#define ICE_LUT_KEYS_CRYPTOCFG_OFFSET 0x80
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/* Non HWKM Targets */
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#define ICE_LUT_KEYS_SW_CRYPTOCFG_R_16 0x2040
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#define ICE_LUT_KEYS_SW_CRYPTOCFG_R_17 0x2044
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#define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_STTS 0x3100
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#define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_MASK 0x3104
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#define ICE_LUT_KEYS_SW_ICE_SEC_IRQ_CLR 0x3108
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#define ICE_STREAM1_PARTIALLY_SET_KEY_USED (1L << 0)
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#define ICE_STREAM2_PARTIALLY_SET_KEY_USED (1L << 1)
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#define ICE_QTIC_DBG_OPEN_EVENT (1L << 30)
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