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Merge "clk: qcom: cliffs: Update clocks as per the latest HW support"

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qctecmdr 2023-10-11 09:56:33 -07:00 committed by Gerrit - the friendly Code Review server
commit ae8e3c97a7
2 changed files with 20 additions and 7 deletions
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18
drivers/clk/qcom/gcc-cliffs.c
View File

@ -594,6 +594,22 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
@ -1130,7 +1146,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_floor_ops,
},
.clkr.vdd_data = {
.vdd_classes = gcc_cliffs_regulators,

9
drivers/clk/qcom/gpucc-cliffs.c
View File

@ -47,12 +47,12 @@ static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
/* 520MHz Configuration */
/* 510MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1b,
.l = 0x1a,
.cal_l = 0x44,
.cal_l_ringosc = 0x44,
.alpha = 0x1555,
.alpha = 0x9000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
@ -202,7 +202,6 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
@ -257,7 +256,6 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
@ -285,7 +283,6 @@ static struct clk_rcg2 gpu_cc_xo_clk_src = {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3_ao,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};