Merge "regulator: amoled: Add IBB spur mitigation support"
This commit is contained in:
qctecmdr
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2ac315a014
@ -8,6 +8,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@ -17,7 +18,7 @@
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#include <linux/regulator/machine.h>
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/* Register definitions */
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#define PERIPH_TYPE 0x04
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#define PERIPH_REVISION4 0x03
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#define IBB_PERIPH_TYPE 0x20
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#define AB_PERIPH_TYPE 0x24
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#define OLEDB_PERIPH_TYPE 0x2C
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@ -44,6 +45,29 @@
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#define FORCE_DUAL_PHASE_BIT BIT(1)
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#define FORCE_SINGLE_PHASE_BIT BIT(0)
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/* IBB SPUR FSM/SQM CTL */
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#define IBB_SPUR_CTL(chip) (chip->ibb_base + 0xB6)
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#define SPUR_FSM_EN BIT(7)
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#define SPUR_SQM_EN BIT(6)
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#define IBB_SPUR_FREQ_CTL(chip) (chip->ibb_base + 0xB7)
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#define FREQ_RES_SEL BIT(0)
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#define IBB_SPUR_FREQ_THRESH_HIGH(i) (chip->ibb_base + 0xB8 + i*2)
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#define IBB_SPUR_FREQ_THRESH_LOW(i) (chip->ibb_base + 0xB9 + i*2)
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#define MAX_SPUR_FREQ_BANDS 3
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#define MAX_SPUR_FREQ_KHZ 248
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#define AMOLED_SDAM_OFFSET 0xB8
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#define SQM_TIMER_LOWER_LIMIT_MS 100
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#define SQM_TIMER_UPPER_LIMIT_MS 10000
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enum {
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SPUR_MITIGATION_DISABLED,
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SPUR_MITIGATION_ENABLED_WITHOUT_SQM,
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SPUR_MITIGATION_ENABLED_WITH_SQM,
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};
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struct amoled_regulator {
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struct regulator_desc rdesc;
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struct regulator_dev *rdev;
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@ -70,11 +94,19 @@ struct ab_regulator {
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struct ibb_regulator {
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struct amoled_regulator vreg;
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u8 subtype;
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u8 rev4;
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/* DT params */
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bool swire_control;
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bool pd_control;
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bool single_phase;
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/* ibb_spur_mitigation params */
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u32 spur_mitigation_level;
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u32 spur_sqm_timer_ms;
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u32 spur_freq_thresh_high[MAX_SPUR_FREQ_BANDS];
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u32 spur_freq_thresh_low[MAX_SPUR_FREQ_BANDS];
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bool spur_freq_res_sel;
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};
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struct qpnp_amoled {
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@ -83,7 +115,7 @@ struct qpnp_amoled {
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struct oledb_regulator oledb;
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struct ab_regulator ab;
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struct ibb_regulator ibb;
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struct nvmem_cell *nvmem_cell;
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/* DT params */
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u32 oledb_base;
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u32 ab_base;
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@ -101,6 +133,19 @@ enum ibb_subtype {
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PM8350B_IBB = 0x04,
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};
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enum ibb_rev4 {
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IBB_ANA_MAJOR_V1 = 0x01,
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IBB_ANA_MAJOR_V2 = 0x02,
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};
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static inline bool is_spur_mitigation_supported(struct ibb_regulator *ibb)
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{
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if ((ibb->subtype == PM8350B_IBB) && (ibb->rev4 >= IBB_ANA_MAJOR_V2))
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return true;
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return false;
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}
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static inline bool is_phase_ctrl_supported(struct ibb_regulator *ibb)
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{
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if (ibb->subtype == PM8350B_IBB)
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@ -540,13 +585,76 @@ static int qpnp_amoled_hw_init(struct qpnp_amoled *chip)
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return 0;
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}
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static int qpnp_amoled_ibb_spur_parse_dt(struct qpnp_amoled *chip, struct device_node *node)
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{
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int freq_array_len, rc, i;
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u32 spur_thres[2*MAX_SPUR_FREQ_BANDS];
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rc = of_property_read_u32(node,
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"qcom,ibb-spur-mitigation-level",
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&chip->ibb.spur_mitigation_level);
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if (rc < 0 || (chip->ibb.spur_mitigation_level == SPUR_MITIGATION_DISABLED)) {
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dev_dbg(chip->dev, "ibb spur mitigation DISABLED!");
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return rc;
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}
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if (chip->ibb.spur_mitigation_level == SPUR_MITIGATION_ENABLED_WITH_SQM) {
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of_property_read_u32(node, "qcom,ibb-spur-sqm-timer-ms",
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&chip->ibb.spur_sqm_timer_ms);
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chip->nvmem_cell = devm_nvmem_cell_get(chip->dev,
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"ibb_spur_sqm_timer");
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if (IS_ERR(chip->nvmem_cell)) {
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rc = PTR_ERR(chip->nvmem_cell);
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if (rc != -EPROBE_DEFER)
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dev_err(chip->dev, "Failed to get nvmem-cells, rc=%d\n", rc);
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return rc;
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}
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}
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/*
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* Read the step size - 1khz or 2khz.
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*
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* NOTE: Even if this is not defined, step size may still be
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* set to 2khz indirectly, if any freq1/2/3 thresh limit
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* is in range: 248khz < f < 496khz.
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*/
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chip->ibb.spur_freq_res_sel = of_property_read_bool(node,
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"qcom,ibb-spur-2khz-step-size");
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freq_array_len = of_property_count_elems_of_size(node,
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"qcom,ibb-spur-freq-thresholds", sizeof(u32));
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if (freq_array_len != 2*MAX_SPUR_FREQ_BANDS) {
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dev_err(chip->dev, "invalid ibb spur freq threshold array size = %d\n",
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freq_array_len);
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chip->ibb.spur_mitigation_level = SPUR_MITIGATION_DISABLED;
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return -EINVAL;
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}
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rc = of_property_read_u32_array(node,
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"qcom,ibb-spur-freq-thresholds", spur_thres, freq_array_len);
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if (rc < 0) {
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dev_err(chip->dev, "failed to read thresholds = %d\n", rc);
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return rc;
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}
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for (i = 0; i < MAX_SPUR_FREQ_BANDS; i++) {
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chip->ibb.spur_freq_thresh_low[i] = spur_thres[2*i];
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chip->ibb.spur_freq_thresh_high[i] = spur_thres[(2*i)+1];
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}
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return rc;
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}
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static int qpnp_amoled_parse_dt(struct qpnp_amoled *chip)
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{
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struct device_node *temp, *node = chip->dev->of_node;
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const __be32 *prop_addr;
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int rc = 0;
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u32 base;
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u8 val[2];
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u8 val[3];
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for_each_available_child_of_node(node, temp) {
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prop_addr = of_get_address(temp, 0, NULL, NULL);
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@ -556,13 +664,13 @@ static int qpnp_amoled_parse_dt(struct qpnp_amoled *chip)
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}
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base = be32_to_cpu(*prop_addr);
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rc = qpnp_amoled_read(chip, base + PERIPH_TYPE, val, 2);
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rc = qpnp_amoled_read(chip, base + PERIPH_REVISION4, val, 3);
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if (rc < 0) {
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pr_err("Couldn't read PERIPH_TYPE for base %x\n", base);
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pr_err("Couldn't read PERIPH_REVISION4 for base %x\n", base);
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return rc;
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}
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switch (val[0]) {
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switch (val[1]) {
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case OLEDB_PERIPH_TYPE:
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chip->oledb_base = base;
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chip->oledb.vreg.node = temp;
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@ -579,7 +687,9 @@ static int qpnp_amoled_parse_dt(struct qpnp_amoled *chip)
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break;
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case IBB_PERIPH_TYPE:
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chip->ibb_base = base;
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chip->ibb.subtype = val[1];
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chip->ibb.subtype = val[2];
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chip->ibb.rev4 = val[0];
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chip->ibb.vreg.node = temp;
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chip->ibb.swire_control = of_property_read_bool(temp,
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"qcom,swire-control");
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@ -587,6 +697,13 @@ static int qpnp_amoled_parse_dt(struct qpnp_amoled *chip)
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"qcom,aod-pd-control");
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chip->ibb.single_phase = of_property_read_bool(temp,
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"qcom,ibb-single-phase");
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if (is_spur_mitigation_supported(&chip->ibb)) {
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rc = qpnp_amoled_ibb_spur_parse_dt(chip, temp);
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if (rc < 0)
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pr_err("Failed to parse ibb_spur_parse_dt\n");
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}
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break;
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default:
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pr_err("Unknown peripheral type 0x%x\n", val[0]);
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@ -597,6 +714,167 @@ static int qpnp_amoled_parse_dt(struct qpnp_amoled *chip)
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return 0;
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}
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static bool is_2khz_step_needed(struct qpnp_amoled *chip)
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{
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u8 i;
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/*
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* If any of the freq1/2/3 band has valid thresh
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* (i.e f_high >= f_low)
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* and freq values is in range of 248khz < f < 496khz
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* then use step_size = 2khz
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*/
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for (i = 0; i < MAX_SPUR_FREQ_BANDS; i++) {
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if ((chip->ibb.spur_freq_thresh_high[i] > MAX_SPUR_FREQ_KHZ) &&
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(chip->ibb.spur_freq_thresh_high[i] < MAX_SPUR_FREQ_KHZ * 2) &&
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(chip->ibb.spur_freq_thresh_high[i] >=
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chip->ibb.spur_freq_thresh_low[i])) {
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return true;
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}
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}
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return false;
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}
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static int qpnp_amoled_ibb_spur_set_thresh(struct qpnp_amoled *chip)
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{
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int i = 0, rc = 0;
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u16 low, high, max, temp = 0;
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if (!chip->ibb.spur_freq_res_sel)
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chip->ibb.spur_freq_res_sel = is_2khz_step_needed(chip);
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rc = qpnp_amoled_masked_write(chip,
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IBB_SPUR_FREQ_CTL(chip),
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FREQ_RES_SEL,
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(chip->ibb.spur_freq_res_sel ? FREQ_RES_SEL : 0));
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if (rc < 0) {
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dev_err(chip->dev, "failed to write IBB_SPUR_CTL register!\n");
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return rc;
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}
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/* Calculate max based on the step size */
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max = MAX_SPUR_FREQ_KHZ * (chip->ibb.spur_freq_res_sel ? 2 : 1);
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for (i = 0; i < MAX_SPUR_FREQ_BANDS; i++) {
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low = chip->ibb.spur_freq_thresh_low[i];
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high = chip->ibb.spur_freq_thresh_high[i];
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if (high < low || low > max || high > max) {
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dev_err(chip->dev, "ibb spur freq band%d threshold invalid!\n",
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(i+1));
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/* Set both thresholds to max to in effect disable it */
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chip->ibb.spur_freq_thresh_high[i] = max;
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chip->ibb.spur_freq_thresh_low[i] = max;
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low = max;
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high = max;
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}
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/*
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*For High threshold, roundoff-to-ceiling for odd frequency
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* with 2khz step
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*/
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temp = high / (chip->ibb.spur_freq_res_sel ? 2 : 1);
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temp += chip->ibb.spur_freq_res_sel ? (high % 2) : 0;
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rc = qpnp_amoled_write(chip, IBB_SPUR_FREQ_THRESH_HIGH(i),
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(u8 *)&temp, 1);
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if (rc < 0) {
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dev_err(chip->dev, "failed to write IBB_SPUR_FREQ_HIGH register!\n");
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return rc;
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}
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/*
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* For Low threshold, roundoff-to-floor for odd frequency
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* with 2khz step
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*/
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temp = low / (chip->ibb.spur_freq_res_sel ? 2 : 1);
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rc = qpnp_amoled_write(chip, IBB_SPUR_FREQ_THRESH_LOW(i),
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(u8 *)&temp, 1);
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if (rc < 0) {
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dev_err(chip->dev, "failed to write IBB_SPUR_FREQ_LOW register!\n");
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return rc;
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}
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}
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return 0;
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}
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static int qpnp_amoled_ibb_spur_set_sqm_timer(struct qpnp_amoled *chip, u16 sqm_timer)
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{
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return nvmem_cell_write(chip->nvmem_cell,
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&sqm_timer,
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sizeof(sqm_timer));
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}
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static int qpnp_amoled_ibb_spur_init(struct qpnp_amoled *chip)
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{
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int rc = 0;
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switch (chip->ibb.spur_mitigation_level) {
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case SPUR_MITIGATION_ENABLED_WITH_SQM:
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/*set SQM mode */
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rc = qpnp_amoled_masked_write(chip, IBB_SPUR_CTL(chip),
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SPUR_SQM_EN,
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SPUR_SQM_EN);
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if (rc < 0) {
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dev_err(chip->dev, "failed to enable spur SQM mode!\n");
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return rc;
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}
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/*set SQM timer if defined */
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if (chip->ibb.spur_sqm_timer_ms > SQM_TIMER_LOWER_LIMIT_MS &&
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chip->ibb.spur_sqm_timer_ms < SQM_TIMER_UPPER_LIMIT_MS) {
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rc = qpnp_amoled_ibb_spur_set_sqm_timer(chip,
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(u16)chip->ibb.spur_sqm_timer_ms);
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if (rc < 0) {
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if (rc != -EPROBE_DEFER)
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dev_err(chip->dev,
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"failed to enable spur SQM timer\n");
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return rc;
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}
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}
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fallthrough;
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case SPUR_MITIGATION_ENABLED_WITHOUT_SQM:
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rc = qpnp_amoled_ibb_spur_set_thresh(chip);
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if (rc < 0) {
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dev_err(chip->dev, "failed to set spur thresholds!\n");
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return rc;
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}
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rc = qpnp_amoled_masked_write(chip, IBB_SPUR_CTL(chip),
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SPUR_FSM_EN,
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SPUR_FSM_EN);
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if (rc < 0) {
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dev_err(chip->dev, "failed to enable spur FSM!\n");
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return rc;
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}
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break;
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case SPUR_MITIGATION_DISABLED:
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default:
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/* disable ibb spur FSM */
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rc = qpnp_amoled_masked_write(chip, IBB_SPUR_CTL(chip),
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SPUR_FSM_EN,
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0);
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if (rc < 0) {
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dev_err(chip->dev, "failed to disable spur FSM!\n");
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return rc;
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}
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}
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return 0;
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}
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static int qpnp_amoled_regulator_probe(struct platform_device *pdev)
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{
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int rc;
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@ -634,6 +912,13 @@ static int qpnp_amoled_regulator_probe(struct platform_device *pdev)
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if (rc < 0)
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dev_err(chip->dev, "Failed to initialize HW rc=%d\n", rc);
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if (is_spur_mitigation_supported(&chip->ibb)) {
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rc = qpnp_amoled_ibb_spur_init(chip);
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if (rc < 0)
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dev_err(chip->dev, "Failed to init ibb spur settings rc=%d\n",
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rc);
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}
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error:
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return rc;
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}
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