net/mlx5e: SHAMPO, reduce TIR indication
SHAMPO is an RQ / WQ feature, an indication was added to the TIR in the first place to enforce suitability between connected TIR and RQ, this enforcement does not exist in current the Firmware implementation and was redundant in the first place. Fixes: 83439f3c37aa ("net/mlx5e: Add HW-GRO offload") Signed-off-by: Ben Ben-Ishay <benishay@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Saeed Mahameed
parent
ad11c4f1d8
commit
99a2b9be07
@ -88,9 +88,6 @@ void mlx5e_tir_builder_build_packet_merge(struct mlx5e_tir_builder *builder,
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(MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - rough_max_l2_l3_hdr_sz) >> 8);
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MLX5_SET(tirc, tirc, lro_timeout_period_usecs, pkt_merge_param->timeout);
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break;
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case MLX5E_PACKET_MERGE_SHAMPO:
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MLX5_SET(tirc, tirc, packet_merge_mask, MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO);
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break;
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default:
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break;
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}
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@ -3616,8 +3616,7 @@ static int set_feature_hw_gro(struct net_device *netdev, bool enable)
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goto out;
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}
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err = mlx5e_safe_switch_params(priv, &new_params,
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mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
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err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
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out:
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mutex_unlock(&priv->state_lock);
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return err;
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@ -3434,7 +3434,6 @@ enum {
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enum {
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MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
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MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
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MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2),
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};
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enum {
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