V_01-00-18
1. Added support for GPIO configuration API
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TC956X
jianzhou
parent
ec5b1e771c
commit
8d374ba749
@ -1,7 +1,7 @@
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# Toshiba Electronic Devices & Storage Corporation TC956X PCIe Ethernet Host Driver
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Release Date: 19 Oct 2021
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Release Date: 21 Oct 2021
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Release Version: V_01-00-17 : Limited-tested version
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Release Version: V_01-00-18 : Limited-tested version
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TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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@ -254,3 +254,7 @@ Default Configuraton:
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1. Added M3 SRAM Debug counters to ethtool statistics.
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2. Added MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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## TC956X_Host_Driver_20211021_V_01-00-18:
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1. Added support for GPIO configuration API
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36
common.h
36
common.h
@ -51,6 +51,8 @@
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* 19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
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* 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* VERSION : 01-00-17
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* 21 Oct 2021 : 1. Added support for GPIO configuration API
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* VERSION : 01-00-18
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*/
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#ifndef __COMMON_H__
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@ -723,10 +725,44 @@ enum packets_types {
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#define NFUNCEN6_OFFSET (0x1530)
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#define NFUNCEN7_OFFSET (0x153C)
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#define NFUNCEN_FUNC0 (0)
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#define NFUNCEN4_GPIO_00 GENMASK(3, 0)
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#define NFUNCEN4_GPIO_00_SHIFT (0)
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#define NFUNCEN4_GPIO_01 GENMASK(7, 4)
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#define NFUNCEN4_GPIO_01_SHIFT (4)
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#define NFUNCEN4_GPIO_02 GENMASK(11, 8)
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#define NFUNCEN4_GPIO_02_SHIFT (8)
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#define NFUNCEN4_GPIO_03 GENMASK(15, 12)
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#define NFUNCEN4_GPIO_03_SHIFT (12)
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#define NFUNCEN4_GPIO_04 GENMASK(19, 16)
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#define NFUNCEN4_GPIO_04_SHIFT (16)
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#define NFUNCEN4_GPIO_05 GENMASK(23, 20)
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#define NFUNCEN4_GPIO_05_SHIFT (20)
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#define NFUNCEN4_GPIO_06 GENMASK(27, 24)
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#define NFUNCEN4_GPIO_06_SHIFT (24)
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#define NFUNCEN5_GPIO_10 GENMASK(3, 0)
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#define NFUNCEN5_GPIO_10_SHIFT (0)
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#define NFUNCEN5_GPIO_11 GENMASK(7, 4)
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#define NFUNCEN5_GPIO_11_SHIFT (4)
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#define NFUNCEN6_GPIO_12 GENMASK(19, 16)
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#define NFUNCEN6_GPIO_12_SHIFT (16)
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#define NIOCFG1_OFFSET (0x1614)
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#define NIOCFG7_OFFSET (0x163C)
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#define NIOEN7_OFFSET (0x173C)
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#define GPIO_00 (0)
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#define GPIO_01 (1)
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#define GPIO_02 (2)
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#define GPIO_03 (3)
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#define GPIO_04 (4)
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#define GPIO_05 (5)
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#define GPIO_06 (6)
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#define GPIO_10 (10)
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#define GPIO_11 (11)
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#define GPIO_12 (12)
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#define GPIO_32 (32)
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/* PCIe registers */
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#define PCIE_OFFSET (0x20000)
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#define PCIE_RANGE_UP_OFFSET_RgOffAddr(no) (PCIE_OFFSET + 0x6200 + (no*0x10))
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@ -71,6 +71,8 @@
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* VERSION : 01-00-16
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* 19 Oct 2021 : 1. Version update
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* VERSION : 01-00-17
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* 21 Oct 2021 : 1. Version update
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* VERSION : 01-00-18
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*/
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#include <linux/clk-provider.h>
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@ -103,7 +105,7 @@ static unsigned int tc956x_port1_interface = ENABLE_SGMII_INTERFACE;
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unsigned int tc956x_port0_filter_phy_pause_frames = DISABLE;
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unsigned int tc956x_port1_filter_phy_pause_frames = DISABLE;
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 1, 7};
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 1, 8};
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/*
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* This struct is used to associate PCI Function of MAC controller on a board,
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@ -72,6 +72,9 @@
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* : 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* : 3. Version update
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* VERSION : 01-00-17
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* 21 Oct 2021 : 1. Added support for GPIO configuration API
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* : 2. Version update
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* VERSION : 01-00-18
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*/
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#ifndef __TC956XMAC_H__
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@ -120,7 +123,7 @@
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#ifdef TC956X
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#define TC956X_RESOURCE_NAME "tc956x_pci-eth"
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#define DRV_MODULE_VERSION "V_01-00-17"
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#define DRV_MODULE_VERSION "V_01-00-18"
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#define TC956X_FW_MAX_SIZE (64*1024)
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#define ATR_AXI4_SLV_BASE 0x0800
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@ -703,5 +706,6 @@ static inline int tc956x_platform_suspend(struct tc956xmac_priv *priv) { return
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static inline int tc956x_platform_resume(struct tc956xmac_priv *priv) { return 0; }
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#endif
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int tc956x_GPIO_OutputConfigPin(struct tc956xmac_priv *priv, u32 gpio_pin, u8 out_value);
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#endif /* __TC956XMAC_H__ */
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115
tc956xmac_main.c
115
tc956xmac_main.c
@ -58,6 +58,8 @@
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* VERSION : 01-00-13
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* 23 Sep 2021 : 1. Capturing RBU status using MAC EVENT Interupt and updating to ethtool statistics for both S/W & IPA DMA channels
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* VERSION : 01-00-14
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* 21 Oct 2021 : 1. Added support for GPIO configuration API
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* VERSION : 01-00-18
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*/
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#include <linux/clk.h>
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@ -207,6 +209,117 @@ static uint16_t mdio_bus_id;
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#define CONFIG_PARAM_NUM ARRAY_SIZE(config_param_list)
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int tc956xmac_rx_parser_configuration(struct tc956xmac_priv *);
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/**
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* tc956x_GPIO_OutputConfigPin - to configure GPIO as output and write the value
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* @priv: driver private structure
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* @gpio_pin: GPIO pin number
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* @out_value : value to write to the GPIO pin. Can be 0 or 1
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* @remarks : Only GPIO0- GPIO06, GPI010-GPIO12 are allowed
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*/
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int tc956x_GPIO_OutputConfigPin(struct tc956xmac_priv *priv, u32 gpio_pin, u8 out_value)
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{
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u32 config, val;
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/* Only GPIO0- GPIO06, GPI010-GPIO12 are allowed */
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switch (gpio_pin) {
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case GPIO_00:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_00;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_00_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_01:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_01;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_01_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_02:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_02;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_02_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_03:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_03;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_03_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_04:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_04;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_04_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_05:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_05;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_05_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_06:
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val = readl(priv->ioaddr + NFUNCEN4_OFFSET);
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val &= ~NFUNCEN4_GPIO_06;
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val |= (NFUNCEN_FUNC0 << NFUNCEN4_GPIO_06_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN4_OFFSET);
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break;
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case GPIO_10:
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val = readl(priv->ioaddr + NFUNCEN5_OFFSET);
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val &= ~NFUNCEN5_GPIO_10;
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val |= (NFUNCEN_FUNC0 << NFUNCEN5_GPIO_10_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN5_OFFSET);
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break;
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case GPIO_11:
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val = readl(priv->ioaddr + NFUNCEN5_OFFSET);
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val &= ~NFUNCEN5_GPIO_11;
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val |= (NFUNCEN_FUNC0 << NFUNCEN5_GPIO_11_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN5_OFFSET);
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break;
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case GPIO_12:
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val = readl(priv->ioaddr + NFUNCEN6_OFFSET);
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val &= ~NFUNCEN6_GPIO_12;
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val |= (NFUNCEN_FUNC0 << NFUNCEN6_GPIO_12_SHIFT);
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writel(val, priv->ioaddr + NFUNCEN6_OFFSET);
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break;
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default :
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netdev_err(priv->dev, "Invalid GPIO pin - %d\n", gpio_pin);
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return -EPERM;
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}
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/* Write data to GPIO pin */
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if(gpio_pin < GPIO_32) {
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config = 1 << gpio_pin;
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val = readl(priv->ioaddr + GPIOO0_OFFSET);
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val &= ~config;
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if(out_value)
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val |= config;
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writel(val, priv->ioaddr + GPIOO0_OFFSET);
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} else {
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config = 1 << (gpio_pin - GPIO_32);
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val = readl(priv->ioaddr + GPIOO1_OFFSET);
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val &= ~config;
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if(out_value)
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val |= config;
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writel(val, priv->ioaddr + GPIOO1_OFFSET);
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}
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/* Configure the GPIO pin in output direction */
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if(gpio_pin < GPIO_32) {
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config = ~(1 << gpio_pin) ;
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val = readl(priv->ioaddr + GPIOE0_OFFSET);
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writel(val & config, priv->ioaddr + GPIOE0_OFFSET);
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} else {
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config = ~(1 << (gpio_pin - GPIO_32)) ;
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val = readl(priv->ioaddr + GPIOE1_OFFSET);
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writel(val & config, priv->ioaddr + GPIOE1_OFFSET);
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}
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return 0;
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}
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/**
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* tc956xmac_verify_args - verify the driver parameters.
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* Description: it checks the driver parameters and set a default in case of
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@ -9863,6 +9976,7 @@ int tc956xmac_dvr_probe(struct device *device,
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priv = netdev_priv(ndev);
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priv->device = device;
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priv->dev = ndev;
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priv->ioaddr = res->addr;
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ret = tc956x_platform_probe(priv, res);
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if (ret) {
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@ -9878,7 +9992,6 @@ int tc956xmac_dvr_probe(struct device *device,
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tc956xmac_set_ethtool_ops(ndev);
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priv->pause = pause;
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priv->plat = plat_dat;
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priv->ioaddr = res->addr;
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#ifdef TC956X
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priv->tc956x_SFR_pci_base_addr = res->tc956x_SFR_pci_base_addr;
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priv->tc956x_SRAM_pci_base_addr = res->tc956x_SRAM_pci_base_addr;
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