V_01-00-17
1. Added M3 SRAM Debug counters to ethtool statistics. 2. Added MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
This commit is contained in:
TC956X
jianzhou
parent
f5792b1dd5
commit
ec5b1e771c
@ -1,7 +1,7 @@
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# Toshiba Electronic Devices & Storage Corporation TC956X PCIe Ethernet Host Driver
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Release Date: 14 Oct 2021
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Release Date: 19 Oct 2021
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Release Version: V_01-00-16 : Limited-tested version
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Release Version: V_01-00-17 : Limited-tested version
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TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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@ -249,3 +249,8 @@ Default Configuraton:
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1. Configuring pause frame control using kernel module parameter also forwarding only Link partner pause frames to Application and filtering PHY pause frames using FRP.
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2. Returning error on disabling Receive Flow Control via ethtool for speed other than 10G in XFI mode.
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## TC956X_Host_Driver_20211019_V_01-00-17:
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1. Added M3 SRAM Debug counters to ethtool statistics.
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2. Added MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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30
common.h
30
common.h
@ -48,6 +48,9 @@
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* VERSION : 01-00-14
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* 14 Oct 2021 : 1. Moving common Macros to common header file
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* VERSION : 01-00-16
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* 19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
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* 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* VERSION : 01-00-17
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*/
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#ifndef __COMMON_H__
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@ -1223,6 +1226,33 @@ struct tc956xmac_extra_stats {
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u64 xpcs_intr_n;
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u64 phy_intr_n;
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u64 sw_msi_n;
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/*MTL Debug counters */
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u64 mtl_tx_underflow[MTL_MAX_TX_QUEUES];
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u64 mtl_rx_miss_pkt_cnt[MTL_MAX_RX_QUEUES];
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u64 mtl_rx_overflow_pkt_cnt[MTL_MAX_RX_QUEUES];
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u64 rxch_watchdog_timer[TC956XMAC_CH_MAX];
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/*m3 SRAM debug counters */
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u64 m3_debug_cnt0;
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u64 m3_debug_cnt1;
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u64 m3_debug_cnt2;
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u64 m3_debug_cnt3;
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u64 m3_debug_cnt4;
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u64 m3_debug_cnt5;
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u64 m3_debug_cnt6;
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u64 m3_debug_cnt7;
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u64 m3_debug_cnt8;
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u64 m3_debug_cnt9;
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u64 m3_debug_cnt10;
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u64 m3_watchdog_exp_cnt;
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u64 m3_watchdog_monitor_cnt;
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u64 m3_debug_cnt13;
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u64 m3_debug_cnt14;
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u64 m3_systick_cnt_upper_value;
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u64 m3_systick_cnt_lower_value;
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u64 m3_tx_timeout_port0;
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u64 m3_tx_timeout_port1;
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u64 m3_debug_cnt19;
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};
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12
dwxgmac2.h
12
dwxgmac2.h
@ -39,6 +39,9 @@
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* 3. Removed IOCTL TC956XMAC_VLAN_STRIP_CONFIG.
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* 4. Removed "Disable VLAN Filter" option in IOCTL TC956XMAC_VLAN_FILTERING.
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* VERSION : 01-00-13
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* 19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
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* 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* VERSION : 01-00-17
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*/
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@ -427,6 +430,10 @@
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#define XGMAC_TXQEN GENMASK(3, 2)
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#define XGMAC_TXQEN_SHIFT 2
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#define XGMAC_TSF BIT(1)
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#define XGMAC_MTL_TXQ_UF_OFFSET(x) (MAC_OFFSET + (0x00001104 + (0x80 * (x))))
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#define XGMAC_MTL_UFPKTCNT_MASK GENMASK(10, 0)
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#define XGMAC_MTL_TXQ_UFPKT_CNT(x) ((XGMAC_MTL_TXQ_UF_OFFSET(x)) & XGMAC_MTL_UFPKTCNT_MASK)
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#define XGMAC_MTL_TXQ_Debug(x) (MAC_OFFSET + (0x00001108 + (0x80 * (x))))
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#define XGMAC_MTL_DEBUG_TXQSTS BIT(4)
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#define XGMAC_MTL_DEBUG_TWCSTS BIT(3)
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@ -454,6 +461,11 @@
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#define XGMAC_RSF BIT(5)
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#define XGMAC_RTC GENMASK(1, 0)
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#define XGMAC_RTC_SHIFT 0
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#define XGMAC_MTL_RXQ_MISS_PKT_OF_CNT_OFFSET(x) (MAC_OFFSET + 0x00001144 + (0x80 * (x)))
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#define XGMAC_OVFPKTCNT_MASK GENMASK(10, 0)
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#define XGMAC_MISPKTCNT_MASK GENMASK(26, 16)
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#define XGMAC_MISPKTCNT_SHIFT 16
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#define XGMAC_MTL_RXQ_Debug(x) (0x00001148 + (0x80 * (x)))
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#define XGMAC_MTL_DEBUG_RXQSTS_MASK GENMASK(5, 4)
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#define XGMAC_MTL_DEBUG_RXQSTS_SHIFT 4
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@ -69,6 +69,8 @@
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: 2. Configuring pause frame control using kernel module parameter also forwarding
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* only Link partner pause frames to Application and filtering PHY pause frames using FRP
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* VERSION : 01-00-16
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* 19 Oct 2021 : 1. Version update
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* VERSION : 01-00-17
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*/
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#include <linux/clk-provider.h>
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@ -101,7 +103,7 @@ static unsigned int tc956x_port1_interface = ENABLE_SGMII_INTERFACE;
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unsigned int tc956x_port0_filter_phy_pause_frames = DISABLE;
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unsigned int tc956x_port1_filter_phy_pause_frames = DISABLE;
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 1, 6};
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 1, 7};
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/*
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* This struct is used to associate PCI Function of MAC controller on a board,
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30
tc956xmac.h
30
tc956xmac.h
@ -68,6 +68,10 @@
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* VERSION : 01-00-15
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* 14 Oct 2021 : 1. Version update
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* VERSION : 01-00-16
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* 19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
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* : 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* : 3. Version update
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* VERSION : 01-00-17
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*/
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#ifndef __TC956XMAC_H__
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@ -116,7 +120,7 @@
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#ifdef TC956X
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#define TC956X_RESOURCE_NAME "tc956x_pci-eth"
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#define DRV_MODULE_VERSION "V_01-00-16"
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#define DRV_MODULE_VERSION "V_01-00-17"
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#define TC956X_FW_MAX_SIZE (64*1024)
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#define ATR_AXI4_SLV_BASE 0x0800
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@ -172,6 +176,30 @@
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#endif
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#define TC956X_M3_SRAM_FW_VER_OFFSET 0x4F900 /* DMEM addrs 0x2000F900 */
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/* M3 Debug Counters in SRAM*/
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#define TC956X_M3_SRAM_DEBUG_CNTS_OFFSET 0x4F800 /* DMEM addrs 0x2000F800 */
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#define DB_CNT_LEN 4 /* Size of each debug counter in bytes */
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#define DB_CNT0 0 /* reserved0 */
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#define DB_CNT1 1 /* reserved1 */
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#define DB_CNT2 2 /* reserved2 */
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#define DB_CNT3 3 /* reserved3 */
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#define DB_CNT4 4 /* reserved4 */
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#define DB_CNT5 5 /* reserved5 */
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#define DB_CNT6 6 /* reserved6 */
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#define DB_CNT7 7 /* reserved7 */
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#define DB_CNT8 8 /* reserved8 */
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#define DB_CNT9 9 /* reserved9 */
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#define DB_CNT10 10 /* reserved10 */
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#define DB_CNT11 11 /* m3 watchdog expiry count*/
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#define DB_CNT12 12 /* m3 watchdog monitor value */
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#define DB_CNT13 13 /* reserved13 */
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#define DB_CNT14 14 /* reserved14 */
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#define DB_CNT15 15 /* m3 systick counter lower 32bits */
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#define DB_CNT16 16 /* m3 systick counter upper 32bits */
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#define DB_CNT17 17 /* m3 transmission timeout indication for port0 */
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#define DB_CNT18 18 /* m3 transmission timeout indication for port1 */
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#define DB_CNT19 19 /* reserved19 */
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#define NRSTCTRL0_RST_ASRT 0x1
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#define NRSTCTRL0_RST_DE_ASRT 0x3
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@ -38,6 +38,9 @@
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* VERSION : 01-00-02
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* 14 Oct 2021 : 1. Returning error on disabling Receive Flow Control via ethtool for speed other than 10G in XFI mode.
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* VERSION : 01-00-16
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* 19 Oct 2021 : 1. Adding M3 SRAM Debug counters to ethtool statistics
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* 2. Adding MTL RX Overflow/packet miss count, TX underflow counts,Rx Watchdog value to ethtool statistics.
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* VERSION : 01-00-17
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*/
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#include <linux/etherdevice.h>
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@ -605,6 +608,59 @@ static const struct tc956xmac_stats tc956xmac_gstrings_stats[] = {
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TC956XMAC_STAT(xpcs_intr_n),
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TC956XMAC_STAT(phy_intr_n),
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TC956XMAC_STAT(sw_msi_n),
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TC956XMAC_STAT(mtl_tx_underflow[0]),
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TC956XMAC_STAT(mtl_tx_underflow[1]),
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TC956XMAC_STAT(mtl_tx_underflow[3]),
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TC956XMAC_STAT(mtl_tx_underflow[4]),
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TC956XMAC_STAT(mtl_tx_underflow[5]),
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TC956XMAC_STAT(mtl_tx_underflow[6]),
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TC956XMAC_STAT(mtl_tx_underflow[7]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[0]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[1]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[3]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[4]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[5]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[6]),
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TC956XMAC_STAT(mtl_rx_miss_pkt_cnt[7]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[0]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[1]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[3]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[4]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[5]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[6]),
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TC956XMAC_STAT(mtl_rx_overflow_pkt_cnt[7]),
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TC956XMAC_STAT(rxch_watchdog_timer[0]),
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TC956XMAC_STAT(rxch_watchdog_timer[1]),
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TC956XMAC_STAT(rxch_watchdog_timer[2]),
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TC956XMAC_STAT(rxch_watchdog_timer[3]),
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TC956XMAC_STAT(rxch_watchdog_timer[4]),
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TC956XMAC_STAT(rxch_watchdog_timer[5]),
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TC956XMAC_STAT(rxch_watchdog_timer[6]),
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TC956XMAC_STAT(rxch_watchdog_timer[7]),
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TC956XMAC_STAT(m3_debug_cnt0),
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TC956XMAC_STAT(m3_debug_cnt1),
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TC956XMAC_STAT(m3_debug_cnt2),
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TC956XMAC_STAT(m3_debug_cnt3),
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TC956XMAC_STAT(m3_debug_cnt4),
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TC956XMAC_STAT(m3_debug_cnt5),
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TC956XMAC_STAT(m3_debug_cnt6),
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TC956XMAC_STAT(m3_debug_cnt7),
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TC956XMAC_STAT(m3_debug_cnt8),
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TC956XMAC_STAT(m3_debug_cnt9),
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TC956XMAC_STAT(m3_debug_cnt10),
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TC956XMAC_STAT(m3_watchdog_exp_cnt),
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TC956XMAC_STAT(m3_watchdog_monitor_cnt),
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TC956XMAC_STAT(m3_debug_cnt13),
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TC956XMAC_STAT(m3_debug_cnt14),
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TC956XMAC_STAT(m3_systick_cnt_upper_value),
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TC956XMAC_STAT(m3_systick_cnt_lower_value),
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TC956XMAC_STAT(m3_tx_timeout_port0),
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TC956XMAC_STAT(m3_tx_timeout_port1),
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TC956XMAC_STAT(m3_debug_cnt19),
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};
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#define TC956XMAC_STATS_LEN ARRAY_SIZE(tc956xmac_gstrings_stats)
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@ -988,6 +1044,74 @@ tc956xmac_set_pauseparam(struct net_device *netdev,
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priv->pause, tx_cnt);
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return 0;
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}
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static void tc956xmac_m3fw_stats_read(struct tc956xmac_priv *priv)
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{
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u32 rx_queues_count = priv->plat->rx_queues_to_use;
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u32 tx_queues_count = priv->plat->tx_queues_to_use;
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u32 chno, reg_val=0;
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for (chno = 0; chno < tx_queues_count; chno++) {
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/* Tx Underflow count may not match with actual value, as it is 11bit value
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accumulation happening only when reading ethool statistics, not after overflow of counter*/
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priv->xstats.mtl_tx_underflow[chno] +=
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readl(priv->ioaddr + XGMAC_MTL_TXQ_UFPKT_CNT(chno));
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}
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for (chno = 0; chno < rx_queues_count; chno++) {
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/* Rx overflow/missed pkt count may not match with actual values, as these are 11bit values
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accumulation happening only when reading ethool statistics, not after overflow of counters*/
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reg_val = readl(priv->ioaddr + XGMAC_MTL_RXQ_MISS_PKT_OF_CNT_OFFSET(chno));
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priv->xstats.mtl_rx_miss_pkt_cnt[chno] += ((reg_val & XGMAC_MISPKTCNT_MASK) >>
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XGMAC_MISPKTCNT_SHIFT);
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priv->xstats.mtl_rx_overflow_pkt_cnt[chno] += (reg_val & XGMAC_OVFPKTCNT_MASK);
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priv->xstats.rxch_watchdog_timer[chno] =
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readl(priv->ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(chno));
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}
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/* Reading M3 Debug Counters*/
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priv->xstats.m3_debug_cnt0 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT0 )));
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priv->xstats.m3_debug_cnt1 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT1 )));
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priv->xstats.m3_debug_cnt2 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT2 )));
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priv->xstats.m3_debug_cnt3 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT3 )));
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priv->xstats.m3_debug_cnt4 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT4 )));
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priv->xstats.m3_debug_cnt5 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT5 )));
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priv->xstats.m3_debug_cnt6 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT6 )));
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priv->xstats.m3_debug_cnt7 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT7 )));
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priv->xstats.m3_debug_cnt8 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT8 )));
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priv->xstats.m3_debug_cnt9 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT9 )));
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priv->xstats.m3_debug_cnt10 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT10 )));
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priv->xstats.m3_watchdog_exp_cnt = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT11 )));
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priv->xstats.m3_watchdog_monitor_cnt = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT12 )));
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priv->xstats.m3_debug_cnt13 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT13 )));
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priv->xstats.m3_debug_cnt14 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT14 )));
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priv->xstats.m3_systick_cnt_upper_value = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT16 )));
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priv->xstats.m3_systick_cnt_lower_value = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT15 )));
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priv->xstats.m3_tx_timeout_port0 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT17 )));
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priv->xstats.m3_tx_timeout_port1 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT18 )));
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priv->xstats.m3_debug_cnt19 = readl(priv->tc956x_SRAM_pci_base_addr +
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(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT19 )));
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}
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static void tc956xmac_get_ethtool_stats(struct net_device *dev,
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struct ethtool_stats *dummy, u64 *data)
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@ -1040,6 +1164,7 @@ static void tc956xmac_get_ethtool_stats(struct net_device *dev,
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tc956xmac_dma_desc_stats(priv, priv->ioaddr);
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}
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}
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tc956xmac_m3fw_stats_read(priv);
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for (i = 0; i < TC956XMAC_STATS_LEN; i++) {
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char *p = (char *)priv + tc956xmac_gstrings_stats[i].stat_offset;
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