drm/omap: work-around for errata i886
DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values) says that FPDLink is sensitive to jitter on the vout clock, and that low PLL M and N values result in more jitter than high M and N values. This patch implements a workaround for the problem by changing the PLL setup to search for clocks starting from high M and N values, instead of low values. This should not cause any functional change, and only reduces the jitter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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@ -215,8 +215,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
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dss_pll_calc_func func, void *data)
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{
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const struct dss_pll_hw *hw = pll->hw;
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int n, n_start, n_stop;
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int m, m_start, m_stop;
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int n, n_min, n_max;
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int m, m_min, m_max;
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unsigned long fint, clkdco;
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unsigned long pll_hw_max;
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unsigned long fint_hw_min, fint_hw_max;
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@ -226,21 +226,22 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
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fint_hw_min = hw->fint_min;
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fint_hw_max = hw->fint_max;
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n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
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n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max);
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n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
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n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max);
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pll_max = pll_max ? pll_max : ULONG_MAX;
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for (n = n_start; n <= n_stop; ++n) {
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/* Try to find high N & M to avoid jitter (DRA7 errata i886) */
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for (n = n_max; n >= n_min; --n) {
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fint = clkin / n;
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m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
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m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
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1ul);
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m_stop = min3((unsigned)(pll_max / fint / 2),
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m_max = min3((unsigned)(pll_max / fint / 2),
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(unsigned)(pll_hw_max / fint / 2),
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hw->m_max);
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for (m = m_start; m <= m_stop; ++m) {
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for (m = m_max; m >= m_min; --m) {
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clkdco = 2 * m * fint;
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if (func(n, m, fint, clkdco, data))
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