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Merge branches 'at91-3.18-cleanup' and 'at91-3.18-dt' into at91-3.18-drivers

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This commit is contained in:
Nicolas Ferre
2014-08-25 15:33:23 +02:00
parent 7d1311b93e 2626063f86 464d6e1863
commit 39333610ba
14 changed files with 77 additions and 331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -345,10 +345,14 @@
};
};
ramc: ramc@ffffe200 {
ramc0: ramc@ffffe200 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe200 0x200
0xffffe800 0x200>;
reg = <0xffffe200 0x200>;
};
ramc1: ramc@ffffe800 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe800 0x200>;
};
pit: timer@fffffd30 {

10
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -96,8 +96,14 @@
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200
0xffffe600 0x200>;
reg = <0xffffe400 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
ramc1: ramc@ffffe600 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe600 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};

2
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -87,6 +87,8 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
pmc: pmc@fffffc00 {

2
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -95,6 +95,8 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
pmc: pmc@fffffc00 {

14
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -402,8 +402,10 @@
};
ramc0: ramc@ffffea00 {
compatible = "atmel,at91sam9g45-ddramc";
compatible = "atmel,sama5d3-ddramc";
reg = <0xffffea00 0x200>;
clocks = <&ddrck>, <&mpddr_clk>;
clock-names = "ddrck", "mpddr";
};
dbgu: serial@ffffee00 {
@ -1170,6 +1172,11 @@
#clock-cells = <0>;
reg = <48>;
};
mpddr_clk: mpddr_clk {
#clock-cells = <0>;
reg = <49>;
};
};
};
@ -1178,6 +1185,11 @@
reg = <0xfffffe00 0x10>;
};
shutdown-controller@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
};
pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;

17
arch/arm/mach-at91/Kconfig
View File

@ -28,6 +28,11 @@ config OLD_CLK_AT91
bool
default AT91_PMC_UNIT && AT91_USE_OLD_CLK
config OLD_IRQ_AT91
bool
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config AT91_SAM9_ALT_RESET
bool
default !ARCH_AT91X40
@ -45,18 +50,16 @@ config HAVE_AT91_SMD
config SOC_AT91SAM9
bool
select AT91_SAM9_TIME
select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config SOC_SAMA5
bool
select AT91_SAM9_TIME
select ATMEL_AIC5_IRQ
select CPU_V7
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select USE_OF
menu "Atmel AT91 System-on-Chip"
@ -70,8 +73,7 @@ config ARCH_AT91X40
depends on !MMU
select CPU_ARM7TDMI
select ARCH_USES_GETTIMEOFFSET
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select OLD_IRQ_AT91
help
Select this if you are using one of Atmel's AT91X40 SoC.
@ -108,11 +110,10 @@ endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select HAVE_AT91_USB_CLK
config SOC_AT91SAM9260

6
arch/arm/mach-at91/Kconfig.non_dt
View File

@ -14,31 +14,37 @@ config ARCH_AT91RM9200
bool "AT91RM9200"
select SOC_AT91RM9200
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9260
bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
select SOC_AT91SAM9260
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9261
bool "AT91SAM9261 or AT91SAM9G10"
select SOC_AT91SAM9261
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9263
bool "AT91SAM9263"
select SOC_AT91SAM9263
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
select SOC_AT91SAM9RL
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9G45
bool "AT91SAM9G45"
select SOC_AT91SAM9G45
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
endchoice

3
arch/arm/mach-at91/Makefile
View File

@ -2,11 +2,12 @@
# Makefile for the linux kernel.
#
obj-y := irq.o gpio.o setup.o sysirq_mask.o
obj-y := gpio.o setup.o sysirq_mask.o
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
obj-$(CONFIG_OLD_CLK_AT91) += clock.o
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o

13
arch/arm/mach-at91/board-dt-rm9200.c
View File

@ -24,17 +24,6 @@
#include "at91_aic.h"
#include "generic.h"
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ /*sentinel*/ }
};
static void __init at91rm9200_dt_init_irq(void)
{
of_irq_init(irq_of_match);
}
static const char *at91rm9200_dt_board_compat[] __initdata = {
"atmel,at91rm9200",
NULL
@ -43,8 +32,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
.init_irq = at91rm9200_dt_init_irq,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END

13
arch/arm/mach-at91/board-dt-sam9.c
View File

@ -34,17 +34,6 @@ static void __init sam9_dt_timer_init(void)
at91sam926x_pit_init();
}
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ /*sentinel*/ }
};
static void __init at91_dt_init_irq(void)
{
of_irq_init(irq_of_match);
}
static const char *at91_dt_board_compat[] __initdata = {
"atmel,at91sam9",
NULL
@ -54,8 +43,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
.init_time = sam9_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91_dt_initialize,
.init_irq = at91_dt_init_irq,
.dt_compat = at91_dt_board_compat,
MACHINE_END

13
arch/arm/mach-at91/board-dt-sama5.c
View File

@ -35,17 +35,6 @@ static void __init sama5_dt_timer_init(void)
at91sam926x_pit_init();
}
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
{ /*sentinel*/ }
};
static void __init at91_dt_init_irq(void)
{
of_irq_init(irq_of_match);
}
static int ksz9021rn_phy_fixup(struct phy_device *phy)
{
int value;
@ -82,9 +71,7 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
.init_time = sama5_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic5_handle_irq,
.init_early = at91_dt_initialize,
.init_irq = at91_dt_init_irq,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_dt_board_compat,
MACHINE_END

270
arch/arm/mach-at91/irq.c
View File

@ -48,11 +48,6 @@ void __iomem *at91_aic_base;
static struct irq_domain *at91_aic_domain;
static struct device_node *at91_aic_np;
static unsigned int n_irqs = NR_AIC_IRQS;
static unsigned long at91_aic_caps = 0;
/* AIC5 introduces a Source Select Register */
#define AT91_AIC_CAP_AIC5 (1 << 0)
#define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5)
#ifdef CONFIG_PM
@ -92,50 +87,14 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
void at91_irq_suspend(void)
{
int bit = -1;
if (has_aic5()) {
/* disable enabled irqs */
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
}
/* enable wakeup irqs */
bit = -1;
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IECR, 1);
}
} else {
at91_aic_write(AT91_AIC_IDCR, *backups);
at91_aic_write(AT91_AIC_IECR, *wakeups);
}
at91_aic_write(AT91_AIC_IDCR, *backups);
at91_aic_write(AT91_AIC_IECR, *wakeups);
}
void at91_irq_resume(void)
{
int bit = -1;
if (has_aic5()) {
/* disable wakeup irqs */
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
}
/* enable irqs disabled for suspend */
bit = -1;
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
at91_aic_write(AT91_AIC5_SSR,
bit & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IECR, 1);
}
} else {
at91_aic_write(AT91_AIC_IDCR, *wakeups);
at91_aic_write(AT91_AIC_IECR, *backups);
}
at91_aic_write(AT91_AIC_IDCR, *wakeups);
at91_aic_write(AT91_AIC_IECR, *backups);
}
#else
@ -169,21 +128,6 @@ at91_aic_handle_irq(struct pt_regs *regs)
handle_IRQ(irqnr, regs);
}
asmlinkage void __exception_irq_entry
at91_aic5_handle_irq(struct pt_regs *regs)
{
u32 irqnr;
u32 irqstat;
irqnr = at91_aic_read(AT91_AIC5_IVR);
irqstat = at91_aic_read(AT91_AIC5_ISR);
if (!irqstat)
at91_aic_write(AT91_AIC5_EOICR, 0);
else
handle_IRQ(irqnr, regs);
}
static void at91_aic_mask_irq(struct irq_data *d)
{
/* Disable interrupt on AIC */
@ -192,15 +136,6 @@ static void at91_aic_mask_irq(struct irq_data *d)
clear_backup(d->hwirq);
}
static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
{
/* Disable interrupt on AIC5 */
at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
/* Update ISR cache */
clear_backup(d->hwirq);
}
static void at91_aic_unmask_irq(struct irq_data *d)
{
/* Enable interrupt on AIC */
@ -209,15 +144,6 @@ static void at91_aic_unmask_irq(struct irq_data *d)
set_backup(d->hwirq);
}
static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
{
/* Enable interrupt on AIC5 */
at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IECR, 1);
/* Update ISR cache */
set_backup(d->hwirq);
}
static void at91_aic_eoi(struct irq_data *d)
{
/*
@ -227,11 +153,6 @@ static void at91_aic_eoi(struct irq_data *d)
at91_aic_write(AT91_AIC_EOICR, 0);
}
static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
{
at91_aic_write(AT91_AIC5_EOICR, 0);
}
static unsigned long *at91_extern_irq;
u32 at91_get_extern_irq(void)
@ -282,16 +203,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
if (srctype < 0)
return srctype;
if (has_aic5()) {
at91_aic_write(AT91_AIC5_SSR,
d->hwirq & AT91_AIC5_INTSEL_MSK);
smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
at91_aic_write(AT91_AIC5_SMR, smr | srctype);
} else {
smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
& ~AT91_AIC_SRCTYPE;
at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
}
smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
return 0;
}
@ -331,177 +244,6 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
}
static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
{
int i;
/*
* Perform 8 End Of Interrupt Command to make sure AIC
* will not Lock out nIRQ
*/
for (i = 0; i < 8; i++)
at91_aic_write(AT91_AIC5_EOICR, 0);
/*
* Spurious Interrupt ID in Spurious Vector Register.
* When there is no current interrupt, the IRQ Vector Register
* reads the value stored in AIC_SPU
*/
at91_aic_write(AT91_AIC5_SPU, spu_vector);
/* No debugging in AIC: Debug (Protect) Control Register */
at91_aic_write(AT91_AIC5_DCR, 0);
/* Disable and clear all interrupts initially */
for (i = 0; i < n_irqs; i++) {
at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
at91_aic_write(AT91_AIC5_IDCR, 1);
at91_aic_write(AT91_AIC5_ICCR, 1);
}
}
#if defined(CONFIG_OF)
static unsigned int *at91_aic_irq_priorities;
static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
/* Put virq number in Source Vector Register */
at91_aic_write(AT91_AIC_SVR(hw), virq);
/* Active Low interrupt, with priority */
at91_aic_write(AT91_AIC_SMR(hw),
AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;
}
static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
/* Put virq number in Source Vector Register */
at91_aic_write(AT91_AIC5_SVR, virq);
/* Active Low interrupt, with priority */
at91_aic_write(AT91_AIC5_SMR,
AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;
}
static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
const u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq, unsigned int *out_type)
{
if (WARN_ON(intsize < 3))
return -EINVAL;
if (WARN_ON(intspec[0] >= n_irqs))
return -EINVAL;
if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
|| (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
return -EINVAL;
*out_hwirq = intspec[0];
*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
at91_aic_irq_priorities[*out_hwirq] = intspec[2];
return 0;
}
static struct irq_domain_ops at91_aic_irq_ops = {
.map = at91_aic_irq_map,
.xlate = at91_aic_irq_domain_xlate,
};
int __init at91_aic_of_common_init(struct device_node *node,
struct device_node *parent)
{
struct property *prop;
const __be32 *p;
u32 val;
at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
* sizeof(*at91_extern_irq), GFP_KERNEL);
if (!at91_extern_irq)
return -ENOMEM;
if (at91_aic_pm_init()) {
kfree(at91_extern_irq);
return -ENOMEM;
}
at91_aic_irq_priorities = kzalloc(n_irqs
* sizeof(*at91_aic_irq_priorities),
GFP_KERNEL);
if (!at91_aic_irq_priorities)
return -ENOMEM;
at91_aic_base = of_iomap(node, 0);
at91_aic_np = node;
at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
&at91_aic_irq_ops, NULL);
if (!at91_aic_domain)
panic("Unable to add AIC irq domain (DT)\n");
of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
if (val >= n_irqs)
pr_warn("AIC: external irq %d >= %d skip it\n",
val, n_irqs);
else
set_bit(val, at91_extern_irq);
}
irq_set_default_host(at91_aic_domain);
return 0;
}
int __init at91_aic_of_init(struct device_node *node,
struct device_node *parent)
{
int err;
err = at91_aic_of_common_init(node, parent);
if (err)
return err;
at91_aic_hw_init(n_irqs);
return 0;
}
int __init at91_aic5_of_init(struct device_node *node,
struct device_node *parent)
{
int err;
at91_aic_caps |= AT91_AIC_CAP_AIC5;
n_irqs = NR_AIC5_IRQS;
at91_aic_chip.irq_ack = at91_aic5_mask_irq;
at91_aic_chip.irq_mask = at91_aic5_mask_irq;
at91_aic_chip.irq_unmask = at91_aic5_unmask_irq;
at91_aic_chip.irq_eoi = at91_aic5_eoi;
at91_aic_irq_ops.map = at91_aic5_irq_map;
err = at91_aic_of_common_init(node, parent);
if (err)
return err;
at91_aic5_hw_init(n_irqs);
return 0;
}
#endif
/*
* Initialize the AIC interrupt controller.
*/

32
arch/arm/mach-at91/pm.c
View File

@ -206,16 +206,19 @@ static int at91_pm_enter(suspend_state_t state)
at91_pinctrl_gpio_suspend();
else
at91_gpio_suspend();
at91_irq_suspend();
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
/* remember all the always-wake irqs */
(at91_pmc_read(AT91_PMC_PCSR)
| (1 << AT91_ID_FIQ)
| (1 << AT91_ID_SYS)
| (at91_get_extern_irq()))
& at91_aic_read(AT91_AIC_IMR),
state);
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
at91_irq_suspend();
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
/* remember all the always-wake irqs */
(at91_pmc_read(AT91_PMC_PCSR)
| (1 << AT91_ID_FIQ)
| (1 << AT91_ID_SYS)
| (at91_get_extern_irq()))
& at91_aic_read(AT91_AIC_IMR),
state);
}
switch (state) {
/*
@ -280,12 +283,17 @@ static int at91_pm_enter(suspend_state_t state)
goto error;
}
pr_debug("AT91: PM - wakeup %08x\n",
at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
pr_debug("AT91: PM - wakeup %08x\n",
at91_aic_read(AT91_AIC_IPR) &
at91_aic_read(AT91_AIC_IMR));
error:
target_state = PM_SUSPEND_ON;
at91_irq_resume();
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
at91_irq_resume();
if (of_have_populated_dt())
at91_pinctrl_gpio_resume();
else

3
arch/arm/mach-at91/setup.c
View File

@ -49,7 +49,8 @@ void __init at91_init_irq_default(void)
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
at91_aic_init(priority, at91_boot_soc.extern_irq);
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
at91_aic_init(priority, at91_boot_soc.extern_irq);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();