net: wwan: t7xx: Data path HW layer
Data Path Modem AP Interface (DPMAIF) HW layer provides HW abstraction for the upper layer (DPMAIF HIF). It implements functions to do the HW configuration, TX/RX control and interrupt handling. Signed-off-by: Haijun Liu <haijun.liu@mediatek.com> Signed-off-by: Chandrashekar Devegowda <chandrashekar.devegowda@intel.com> Co-developed-by: Ricardo Martinez <ricardo.martinez@linux.intel.com> Signed-off-by: Ricardo Martinez <ricardo.martinez@linux.intel.com> Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Haijun Liu
committed by
David S. Miller
David S. Miller
parent
61b7a2916a
commit
33f78ab5a3
1283
drivers/net/wwan/t7xx/t7xx_dpmaif.c
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1283
drivers/net/wwan/t7xx/t7xx_dpmaif.c
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File diff suppressed because it is too large
Load Diff
179
drivers/net/wwan/t7xx/t7xx_dpmaif.h
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179
drivers/net/wwan/t7xx/t7xx_dpmaif.h
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@ -0,0 +1,179 @@
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Amir Hanania <amir.hanania@intel.com>
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
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* Eliot Lee <eliot.lee@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#ifndef __T7XX_DPMAIF_H__
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#define __T7XX_DPMAIF_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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#define DPMAIF_DL_PIT_SEQ_VALUE 251
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#define DPMAIF_UL_DRB_SIZE_WORD 4
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#define DPMAIF_MAX_CHECK_COUNT 1000000
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#define DPMAIF_CHECK_TIMEOUT_US 10000
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#define DPMAIF_CHECK_INIT_TIMEOUT_US 100000
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#define DPMAIF_CHECK_DELAY_US 10
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#define DPMAIF_RXQ_NUM 2
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#define DPMAIF_TXQ_NUM 5
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struct dpmaif_isr_en_mask {
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unsigned int ap_ul_l2intr_en_msk;
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unsigned int ap_dl_l2intr_en_msk;
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unsigned int ap_udl_ip_busy_en_msk;
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unsigned int ap_dl_l2intr_err_en_msk;
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};
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struct dpmaif_ul {
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bool que_started;
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unsigned char reserved[3];
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dma_addr_t drb_base;
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unsigned int drb_size_cnt;
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};
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struct dpmaif_dl {
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bool que_started;
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unsigned char reserved[3];
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dma_addr_t pit_base;
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unsigned int pit_size_cnt;
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dma_addr_t bat_base;
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unsigned int bat_size_cnt;
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dma_addr_t frg_base;
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unsigned int frg_size_cnt;
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unsigned int pit_seq;
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};
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struct dpmaif_hw_info {
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struct device *dev;
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void __iomem *pcie_base;
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struct dpmaif_dl dl_que[DPMAIF_RXQ_NUM];
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struct dpmaif_ul ul_que[DPMAIF_TXQ_NUM];
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struct dpmaif_isr_en_mask isr_en_mask;
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};
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/* DPMAIF HW Initialization parameter structure */
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struct dpmaif_hw_params {
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/* UL part */
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dma_addr_t drb_base_addr[DPMAIF_TXQ_NUM];
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unsigned int drb_size_cnt[DPMAIF_TXQ_NUM];
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/* DL part */
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dma_addr_t pkt_bat_base_addr[DPMAIF_RXQ_NUM];
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unsigned int pkt_bat_size_cnt[DPMAIF_RXQ_NUM];
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dma_addr_t frg_bat_base_addr[DPMAIF_RXQ_NUM];
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unsigned int frg_bat_size_cnt[DPMAIF_RXQ_NUM];
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dma_addr_t pit_base_addr[DPMAIF_RXQ_NUM];
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unsigned int pit_size_cnt[DPMAIF_RXQ_NUM];
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};
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enum dpmaif_hw_intr_type {
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DPF_INTR_INVALID_MIN,
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DPF_INTR_UL_DONE,
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DPF_INTR_UL_DRB_EMPTY,
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DPF_INTR_UL_MD_NOTREADY,
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DPF_INTR_UL_MD_PWR_NOTREADY,
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DPF_INTR_UL_LEN_ERR,
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DPF_INTR_DL_DONE,
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DPF_INTR_DL_SKB_LEN_ERR,
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DPF_INTR_DL_BATCNT_LEN_ERR,
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DPF_INTR_DL_PITCNT_LEN_ERR,
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DPF_INTR_DL_PKT_EMPTY_SET,
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DPF_INTR_DL_FRG_EMPTY_SET,
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DPF_INTR_DL_MTU_ERR,
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DPF_INTR_DL_FRGCNT_LEN_ERR,
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DPF_INTR_DL_Q0_PITCNT_LEN_ERR,
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DPF_INTR_DL_Q1_PITCNT_LEN_ERR,
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DPF_INTR_DL_HPC_ENT_TYPE_ERR,
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DPF_INTR_DL_Q0_DONE,
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DPF_INTR_DL_Q1_DONE,
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DPF_INTR_INVALID_MAX
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};
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#define DPF_RX_QNO0 0
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#define DPF_RX_QNO1 1
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#define DPF_RX_QNO_DFT DPF_RX_QNO0
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struct dpmaif_hw_intr_st_para {
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unsigned int intr_cnt;
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enum dpmaif_hw_intr_type intr_types[DPF_INTR_INVALID_MAX - 1];
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unsigned int intr_queues[DPF_INTR_INVALID_MAX - 1];
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};
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#define DPMAIF_HW_BAT_REMAIN 64
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#define DPMAIF_HW_BAT_PKTBUF (128 * 28)
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#define DPMAIF_HW_FRG_PKTBUF 128
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#define DPMAIF_HW_BAT_RSVLEN 64
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#define DPMAIF_HW_PKT_BIDCNT 1
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#define DPMAIF_HW_MTU_SIZE (3 * 1024 + 8)
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#define DPMAIF_HW_CHK_BAT_NUM 62
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#define DPMAIF_HW_CHK_FRG_NUM 3
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#define DPMAIF_HW_CHK_PIT_NUM (2 * DPMAIF_HW_CHK_BAT_NUM)
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#define DP_UL_INT_DONE_OFFSET 0
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#define DP_UL_INT_QDONE_MSK GENMASK(4, 0)
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#define DP_UL_INT_EMPTY_MSK GENMASK(9, 5)
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#define DP_UL_INT_MD_NOTREADY_MSK GENMASK(14, 10)
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#define DP_UL_INT_MD_PWR_NOTREADY_MSK GENMASK(19, 15)
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#define DP_UL_INT_ERR_MSK GENMASK(24, 20)
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#define DP_DL_INT_QDONE_MSK BIT(0)
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#define DP_DL_INT_SKB_LEN_ERR BIT(1)
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#define DP_DL_INT_BATCNT_LEN_ERR BIT(2)
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#define DP_DL_INT_PITCNT_LEN_ERR BIT(3)
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#define DP_DL_INT_PKT_EMPTY_MSK BIT(4)
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#define DP_DL_INT_FRG_EMPTY_MSK BIT(5)
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#define DP_DL_INT_MTU_ERR_MSK BIT(6)
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#define DP_DL_INT_FRG_LEN_ERR_MSK BIT(7)
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#define DP_DL_INT_Q0_PITCNT_LEN_ERR BIT(8)
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#define DP_DL_INT_Q1_PITCNT_LEN_ERR BIT(9)
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#define DP_DL_INT_HPC_ENT_TYPE_ERR BIT(10)
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#define DP_DL_INT_Q0_DONE BIT(13)
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#define DP_DL_INT_Q1_DONE BIT(14)
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#define DP_DL_Q0_STATUS_MASK (DP_DL_INT_Q0_PITCNT_LEN_ERR | DP_DL_INT_Q0_DONE)
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#define DP_DL_Q1_STATUS_MASK (DP_DL_INT_Q1_PITCNT_LEN_ERR | DP_DL_INT_Q1_DONE)
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int t7xx_dpmaif_hw_init(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_param);
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int t7xx_dpmaif_hw_stop_all_txq(struct dpmaif_hw_info *hw_info);
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int t7xx_dpmaif_hw_stop_all_rxq(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_start_hw(struct dpmaif_hw_info *hw_info);
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int t7xx_dpmaif_hw_get_intr_cnt(struct dpmaif_hw_info *hw_info,
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struct dpmaif_hw_intr_st_para *para, int qno);
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void t7xx_dpmaif_unmask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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void t7xx_dpmaif_ul_update_hw_drb_cnt(struct dpmaif_hw_info *hw_info, unsigned int q_num,
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unsigned int drb_entry_cnt);
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int t7xx_dpmaif_dl_snd_hw_bat_cnt(struct dpmaif_hw_info *hw_info, unsigned int bat_entry_cnt);
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int t7xx_dpmaif_dl_snd_hw_frg_cnt(struct dpmaif_hw_info *hw_info, unsigned int frg_entry_cnt);
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int t7xx_dpmaif_dlq_add_pit_remain_cnt(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx,
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unsigned int pit_remain_cnt);
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void t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info,
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unsigned int qno);
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void t7xx_dpmaif_dlq_unmask_rx_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
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bool t7xx_dpmaif_ul_clr_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
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void t7xx_dpmaif_ul_clr_all_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_clr_all_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_clr_ip_busy_sts(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_unmask_batcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
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void t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
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unsigned int t7xx_dpmaif_ul_get_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_bat_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_bat_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_get_frg_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
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unsigned int t7xx_dpmaif_dl_dlq_pit_get_wr_idx(struct dpmaif_hw_info *hw_info,
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unsigned int dlq_pit_idx);
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#endif /* __T7XX_DPMAIF_H__ */
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@ -134,4 +134,217 @@ enum t7xx_int {
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CLDMA3_INT,
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};
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/* DPMA definitions */
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#define DPMAIF_PD_BASE 0x1022d000
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#define BASE_DPMAIF_UL DPMAIF_PD_BASE
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#define BASE_DPMAIF_DL (DPMAIF_PD_BASE + 0x100)
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#define BASE_DPMAIF_AP_MISC (DPMAIF_PD_BASE + 0x400)
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#define BASE_DPMAIF_MMW_HPC (DPMAIF_PD_BASE + 0x600)
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#define BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX (DPMAIF_PD_BASE + 0x900)
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#define BASE_DPMAIF_PD_SRAM_DL (DPMAIF_PD_BASE + 0xc00)
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#define BASE_DPMAIF_PD_SRAM_UL (DPMAIF_PD_BASE + 0xd00)
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#define DPMAIF_AO_BASE 0x10014000
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#define BASE_DPMAIF_AO_UL DPMAIF_AO_BASE
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#define BASE_DPMAIF_AO_DL (DPMAIF_AO_BASE + 0x400)
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#define DPMAIF_UL_ADD_DESC (BASE_DPMAIF_UL + 0x00)
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#define DPMAIF_UL_CHK_BUSY (BASE_DPMAIF_UL + 0x88)
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#define DPMAIF_UL_RESERVE_AO_RW (BASE_DPMAIF_UL + 0xac)
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#define DPMAIF_UL_ADD_DESC_CH0 (BASE_DPMAIF_UL + 0xb0)
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#define DPMAIF_DL_BAT_INIT (BASE_DPMAIF_DL + 0x00)
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#define DPMAIF_DL_BAT_ADD (BASE_DPMAIF_DL + 0x04)
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#define DPMAIF_DL_BAT_INIT_CON0 (BASE_DPMAIF_DL + 0x08)
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#define DPMAIF_DL_BAT_INIT_CON1 (BASE_DPMAIF_DL + 0x0c)
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#define DPMAIF_DL_BAT_INIT_CON2 (BASE_DPMAIF_DL + 0x10)
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#define DPMAIF_DL_BAT_INIT_CON3 (BASE_DPMAIF_DL + 0x50)
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#define DPMAIF_DL_CHK_BUSY (BASE_DPMAIF_DL + 0xb4)
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#define DPMAIF_AP_L2TISAR0 (BASE_DPMAIF_AP_MISC + 0x00)
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#define DPMAIF_AP_APDL_L2TISAR0 (BASE_DPMAIF_AP_MISC + 0x50)
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#define DPMAIF_AP_IP_BUSY (BASE_DPMAIF_AP_MISC + 0x60)
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#define DPMAIF_AP_CG_EN (BASE_DPMAIF_AP_MISC + 0x68)
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#define DPMAIF_AP_OVERWRITE_CFG (BASE_DPMAIF_AP_MISC + 0x90)
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#define DPMAIF_AP_MEM_CLR (BASE_DPMAIF_AP_MISC + 0x94)
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#define DPMAIF_AP_ALL_L2TISAR0_MASK GENMASK(31, 0)
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#define DPMAIF_AP_APDL_ALL_L2TISAR0_MASK GENMASK(31, 0)
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#define DPMAIF_AP_IP_BUSY_MASK GENMASK(31, 0)
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#define DPMAIF_AO_UL_INIT_SET (BASE_DPMAIF_AO_UL + 0x0)
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#define DPMAIF_AO_UL_CHNL_ARB0 (BASE_DPMAIF_AO_UL + 0x1c)
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#define DPMAIF_AO_UL_AP_L2TIMR0 (BASE_DPMAIF_AO_UL + 0x80)
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#define DPMAIF_AO_UL_AP_L2TIMCR0 (BASE_DPMAIF_AO_UL + 0x84)
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#define DPMAIF_AO_UL_AP_L2TIMSR0 (BASE_DPMAIF_AO_UL + 0x88)
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#define DPMAIF_AO_UL_AP_L1TIMR0 (BASE_DPMAIF_AO_UL + 0x8c)
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#define DPMAIF_AO_UL_APDL_L2TIMR0 (BASE_DPMAIF_AO_UL + 0x90)
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#define DPMAIF_AO_UL_APDL_L2TIMCR0 (BASE_DPMAIF_AO_UL + 0x94)
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#define DPMAIF_AO_UL_APDL_L2TIMSR0 (BASE_DPMAIF_AO_UL + 0x98)
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#define DPMAIF_AO_AP_DLUL_IP_BUSY_MASK (BASE_DPMAIF_AO_UL + 0x9c)
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#define DPMAIF_AO_UL_CHNL0_CON0 (BASE_DPMAIF_PD_SRAM_UL + 0x10)
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#define DPMAIF_AO_UL_CHNL0_CON1 (BASE_DPMAIF_PD_SRAM_UL + 0x14)
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#define DPMAIF_AO_UL_CHNL0_CON2 (BASE_DPMAIF_PD_SRAM_UL + 0x18)
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#define DPMAIF_AO_UL_CH0_STA (BASE_DPMAIF_PD_SRAM_UL + 0x70)
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#define DPMAIF_AO_DL_INIT_SET (BASE_DPMAIF_AO_DL + 0x00)
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#define DPMAIF_AO_DL_IRQ_MASK (BASE_DPMAIF_AO_DL + 0x0c)
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#define DPMAIF_AO_DL_DLQPIT_INIT_CON5 (BASE_DPMAIF_AO_DL + 0x28)
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#define DPMAIF_AO_DL_DLQPIT_TRIG_THRES (BASE_DPMAIF_AO_DL + 0x34)
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#define DPMAIF_AO_DL_PKTINFO_CON0 (BASE_DPMAIF_PD_SRAM_DL + 0x00)
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#define DPMAIF_AO_DL_PKTINFO_CON1 (BASE_DPMAIF_PD_SRAM_DL + 0x04)
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#define DPMAIF_AO_DL_PKTINFO_CON2 (BASE_DPMAIF_PD_SRAM_DL + 0x08)
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#define DPMAIF_AO_DL_RDY_CHK_THRES (BASE_DPMAIF_PD_SRAM_DL + 0x0c)
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#define DPMAIF_AO_DL_RDY_CHK_FRG_THRES (BASE_DPMAIF_PD_SRAM_DL + 0x10)
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#define DPMAIF_AO_DL_DLQ_AGG_CFG (BASE_DPMAIF_PD_SRAM_DL + 0x20)
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#define DPMAIF_AO_DL_DLQPIT_TIMEOUT0 (BASE_DPMAIF_PD_SRAM_DL + 0x24)
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#define DPMAIF_AO_DL_DLQPIT_TIMEOUT1 (BASE_DPMAIF_PD_SRAM_DL + 0x28)
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#define DPMAIF_AO_DL_HPC_CNTL (BASE_DPMAIF_PD_SRAM_DL + 0x38)
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#define DPMAIF_AO_DL_PIT_SEQ_END (BASE_DPMAIF_PD_SRAM_DL + 0x40)
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#define DPMAIF_AO_DL_BAT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xd8)
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#define DPMAIF_AO_DL_BAT_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xdc)
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#define DPMAIF_AO_DL_PIT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xec)
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#define DPMAIF_AO_DL_PIT_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0x60)
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#define DPMAIF_AO_DL_FRGBAT_RD_IDX (BASE_DPMAIF_PD_SRAM_DL + 0x78)
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#define DPMAIF_AO_DL_DLQ_WR_IDX (BASE_DPMAIF_PD_SRAM_DL + 0xa4)
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#define DPMAIF_HPC_INTR_MASK (BASE_DPMAIF_MMW_HPC + 0x0f4)
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#define DPMA_HPC_ALL_INT_MASK GENMASK(15, 0)
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#define DPMAIF_HPC_DLQ_PATH_MODE 3
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#define DPMAIF_HPC_ADD_MODE_DF 0
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#define DPMAIF_HPC_TOTAL_NUM 8
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#define DPMAIF_HPC_MAX_TOTAL_NUM 8
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#define DPMAIF_DL_DLQPIT_INIT (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x00)
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#define DPMAIF_DL_DLQPIT_ADD (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x10)
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#define DPMAIF_DL_DLQPIT_INIT_CON0 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x14)
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#define DPMAIF_DL_DLQPIT_INIT_CON1 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x18)
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#define DPMAIF_DL_DLQPIT_INIT_CON2 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x1c)
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#define DPMAIF_DL_DLQPIT_INIT_CON3 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x20)
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#define DPMAIF_DL_DLQPIT_INIT_CON4 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x24)
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#define DPMAIF_DL_DLQPIT_INIT_CON5 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x28)
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#define DPMAIF_DL_DLQPIT_INIT_CON6 (BASE_DPMAIF_DL_DLQ_REMOVEAO_IDX + 0x2c)
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#define DPMAIF_ULQSAR_n(q) (DPMAIF_AO_UL_CHNL0_CON0 + 0x10 * (q))
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#define DPMAIF_UL_DRBSIZE_ADDRH_n(q) (DPMAIF_AO_UL_CHNL0_CON1 + 0x10 * (q))
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#define DPMAIF_UL_DRB_ADDRH_n(q) (DPMAIF_AO_UL_CHNL0_CON2 + 0x10 * (q))
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#define DPMAIF_ULQ_STA0_n(q) (DPMAIF_AO_UL_CH0_STA + 0x04 * (q))
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#define DPMAIF_ULQ_ADD_DESC_CH_n(q) (DPMAIF_UL_ADD_DESC_CH0 + 0x04 * (q))
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#define DPMAIF_UL_DRB_RIDX_MSK GENMASK(31, 16)
|
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#define DPMAIF_AP_RGU_ASSERT 0x10001150
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#define DPMAIF_AP_RGU_DEASSERT 0x10001154
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#define DPMAIF_AP_RST_BIT BIT(2)
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#define DPMAIF_AP_AO_RGU_ASSERT 0x10001140
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#define DPMAIF_AP_AO_RGU_DEASSERT 0x10001144
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#define DPMAIF_AP_AO_RST_BIT BIT(6)
|
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|
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/* DPMAIF init/restore */
|
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#define DPMAIF_UL_ADD_NOT_READY BIT(31)
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#define DPMAIF_UL_ADD_UPDATE BIT(31)
|
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#define DPMAIF_UL_ADD_COUNT_MASK GENMASK(15, 0)
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#define DPMAIF_UL_ALL_QUE_ARB_EN GENMASK(11, 8)
|
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|
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#define DPMAIF_DL_ADD_UPDATE BIT(31)
|
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#define DPMAIF_DL_ADD_NOT_READY BIT(31)
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#define DPMAIF_DL_FRG_ADD_UPDATE BIT(16)
|
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#define DPMAIF_DL_ADD_COUNT_MASK GENMASK(15, 0)
|
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|
||||
#define DPMAIF_DL_BAT_INIT_ALLSET BIT(0)
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#define DPMAIF_DL_BAT_FRG_INIT BIT(16)
|
||||
#define DPMAIF_DL_BAT_INIT_EN BIT(31)
|
||||
#define DPMAIF_DL_BAT_INIT_NOT_READY BIT(31)
|
||||
#define DPMAIF_DL_BAT_INIT_ONLY_ENABLE_BIT 0
|
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|
||||
#define DPMAIF_DL_PIT_INIT_ALLSET BIT(0)
|
||||
#define DPMAIF_DL_PIT_INIT_EN BIT(31)
|
||||
#define DPMAIF_DL_PIT_INIT_NOT_READY BIT(31)
|
||||
|
||||
#define DPMAIF_BAT_REMAIN_SZ_BASE 16
|
||||
#define DPMAIF_BAT_BUFFER_SZ_BASE 128
|
||||
#define DPMAIF_FRG_BUFFER_SZ_BASE 128
|
||||
|
||||
#define DLQ_PIT_IDX_SIZE 0x20
|
||||
|
||||
#define DPMAIF_PIT_SIZE_MSK GENMASK(17, 0)
|
||||
|
||||
#define DPMAIF_PIT_REM_CNT_MSK GENMASK(17, 0)
|
||||
|
||||
#define DPMAIF_BAT_EN_MSK BIT(16)
|
||||
#define DPMAIF_FRG_EN_MSK BIT(28)
|
||||
#define DPMAIF_BAT_SIZE_MSK GENMASK(15, 0)
|
||||
|
||||
#define DPMAIF_BAT_BID_MAXCNT_MSK GENMASK(31, 16)
|
||||
#define DPMAIF_BAT_REMAIN_MINSZ_MSK GENMASK(15, 8)
|
||||
#define DPMAIF_PIT_CHK_NUM_MSK GENMASK(31, 24)
|
||||
#define DPMAIF_BAT_BUF_SZ_MSK GENMASK(16, 8)
|
||||
#define DPMAIF_FRG_BUF_SZ_MSK GENMASK(16, 8)
|
||||
#define DPMAIF_BAT_RSV_LEN_MSK GENMASK(7, 0)
|
||||
#define DPMAIF_PKT_ALIGN_MSK GENMASK(23, 22)
|
||||
|
||||
#define DPMAIF_BAT_CHECK_THRES_MSK GENMASK(21, 16)
|
||||
#define DPMAIF_FRG_CHECK_THRES_MSK GENMASK(7, 0)
|
||||
|
||||
#define DPMAIF_PKT_ALIGN_EN BIT(23)
|
||||
|
||||
#define DPMAIF_DRB_SIZE_MSK GENMASK(15, 0)
|
||||
|
||||
#define DPMAIF_DL_RD_WR_IDX_MSK GENMASK(17, 0)
|
||||
|
||||
/* DPMAIF_UL_CHK_BUSY */
|
||||
#define DPMAIF_UL_IDLE_STS BIT(11)
|
||||
/* DPMAIF_DL_CHK_BUSY */
|
||||
#define DPMAIF_DL_IDLE_STS BIT(23)
|
||||
/* DPMAIF_AO_DL_RDY_CHK_THRES */
|
||||
#define DPMAIF_DL_PKT_CHECKSUM_EN BIT(31)
|
||||
#define DPMAIF_PORT_MODE_PCIE BIT(30)
|
||||
#define DPMAIF_DL_BURST_PIT_EN BIT(13)
|
||||
/* DPMAIF_DL_BAT_INIT_CON1 */
|
||||
#define DPMAIF_DL_BAT_CACHE_PRI BIT(22)
|
||||
/* DPMAIF_AP_MEM_CLR */
|
||||
#define DPMAIF_MEM_CLR BIT(0)
|
||||
/* DPMAIF_AP_OVERWRITE_CFG */
|
||||
#define DPMAIF_SRAM_SYNC BIT(0)
|
||||
/* DPMAIF_AO_UL_INIT_SET */
|
||||
#define DPMAIF_UL_INIT_DONE BIT(0)
|
||||
/* DPMAIF_AO_DL_INIT_SET */
|
||||
#define DPMAIF_DL_INIT_DONE BIT(0)
|
||||
/* DPMAIF_AO_DL_PIT_SEQ_END */
|
||||
#define DPMAIF_DL_PIT_SEQ_MSK GENMASK(7, 0)
|
||||
/* DPMAIF_UL_RESERVE_AO_RW */
|
||||
#define DPMAIF_PCIE_MODE_SET_VALUE 0x55
|
||||
/* DPMAIF_AP_CG_EN */
|
||||
#define DPMAIF_CG_EN 0x7f
|
||||
|
||||
#define DPMAIF_UDL_IP_BUSY BIT(0)
|
||||
#define DPMAIF_DL_INT_DLQ0_QDONE BIT(8)
|
||||
#define DPMAIF_DL_INT_DLQ1_QDONE BIT(9)
|
||||
#define DPMAIF_DL_INT_DLQ0_PITCNT_LEN BIT(10)
|
||||
#define DPMAIF_DL_INT_DLQ1_PITCNT_LEN BIT(11)
|
||||
#define DPMAIF_DL_INT_Q2TOQ1 BIT(24)
|
||||
#define DPMAIF_DL_INT_Q2APTOP BIT(25)
|
||||
|
||||
#define DPMAIF_DLQ_LOW_TIMEOUT_THRES_MKS GENMASK(15, 0)
|
||||
#define DPMAIF_DLQ_HIGH_TIMEOUT_THRES_MSK GENMASK(31, 16)
|
||||
|
||||
/* DPMAIF DLQ HW configure */
|
||||
#define DPMAIF_AGG_MAX_LEN_DF 65535
|
||||
#define DPMAIF_AGG_TBL_ENT_NUM_DF 50
|
||||
#define DPMAIF_HASH_PRIME_DF 13
|
||||
#define DPMAIF_MID_TIMEOUT_THRES_DF 100
|
||||
#define DPMAIF_DLQ_TIMEOUT_THRES_DF 100
|
||||
#define DPMAIF_DLQ_PRS_THRES_DF 10
|
||||
#define DPMAIF_DLQ_HASH_BIT_CHOOSE_DF 0
|
||||
|
||||
#define DPMAIF_DLQPIT_EN_MSK BIT(20)
|
||||
#define DPMAIF_DLQPIT_CHAN_OFS 16
|
||||
#define DPMAIF_ADD_DLQ_PIT_CHAN_OFS 20
|
||||
|
||||
#endif /* __T7XX_REG_H__ */
|
||||
|
||||
Reference in New Issue
Block a user