218325370e
By default, QorIQ SoC's RCPM register block is Big Endian. But there are some exceptions, such as LS1088A and LS2088A, are Little Endian. So add this optional property to help identify them. Actually LS2021A and other Layerscapes won't totally follow Chassis 2.1, so separate them from powerpc SoC. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Li Yang <leoyang.li@nxp.com>
70 lines
2.4 KiB
Plaintext
70 lines
2.4 KiB
Plaintext
* Run Control and Power Management
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-------------------------------------------
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The RCPM performs all device-level tasks associated with device run control
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and power management.
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Required properites:
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- reg : Offset and length of the register set of the RCPM block.
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- #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
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fsl,rcpm-wakeup property.
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- compatible : Must contain a chip-specific RCPM block compatible string
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and (if applicable) may contain a chassis-version RCPM compatible
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string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
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such as:
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* "fsl,p2041-rcpm"
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* "fsl,p5020-rcpm"
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* "fsl,t4240-rcpm"
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Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
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such as:
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* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
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* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
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* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
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* "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm
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All references to "1.0" and "2.0" refer to the QorIQ chassis version to
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which the chip complies.
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Chassis Version Example Chips
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--------------- -------------------------------
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1.0 p4080, p5020, p5040, p2041, p3041
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2.0 t4240, b4860, b4420
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2.1 t1040,
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2.1+ ls1021a, ls1012a, ls1043a, ls1046a
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Optional properties:
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- little-endian : RCPM register block is Little Endian. Without it RCPM
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will be Big Endian (default case).
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Example:
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The RCPM node for T4240:
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rcpm: global-utilities@e2000 {
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compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
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reg = <0xe2000 0x1000>;
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#fsl,rcpm-wakeup-cells = <2>;
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};
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* Freescale RCPM Wakeup Source Device Tree Bindings
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-------------------------------------------
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Required fsl,rcpm-wakeup property should be added to a device node if the device
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can be used as a wakeup source.
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- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
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register cells. The number of IPPDEXPCR register cells is defined in
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"#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
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the bit mask that should be set in IPPDEXPCR0, and the second register
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cell is for IPPDEXPCR1, and so on.
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Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
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mechanism for keeping certain blocks awake during STANDBY and MEM, in
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order to use them as wake-up sources.
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Example:
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lpuart0: serial@2950000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2950000 0x0 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
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};
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