865d3a9afe
Mark the relevant functions noinstr, use the plain non-instrumented MSR accessors. The only odd part is the instrumentation_begin()/end() pair around the indirect machine_check_vector() call as objtool can't figure that out. The possible invoked functions are annotated correctly. Also use notrace variant of nmi_enter/exit(). If MCEs happen then hardware latency tracing is the least of the worries. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Andy Lutomirski <luto@kernel.org> Link: https://lkml.kernel.org/r/20200505135315.476734898@linutronix.de
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* IDT Winchip specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/hardirq.h>
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#include <asm/processor.h>
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#include <asm/traps.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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#include "internal.h"
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/* Machine check handler for WinChip C6: */
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static noinstr void winchip_machine_check(struct pt_regs *regs)
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{
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instrumentation_begin();
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pr_emerg("CPU0: Machine Check Exception.\n");
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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instrumentation_end();
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}
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/* Set up machine check reporting on the Winchip C6 series */
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void winchip_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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machine_check_vector = winchip_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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rdmsr(MSR_IDT_FCR1, lo, hi);
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lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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lo &= ~(1<<4); /* Enable MCE */
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wrmsr(MSR_IDT_FCR1, lo, hi);
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cr4_set_bits(X86_CR4_MCE);
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pr_info("Winchip machine check reporting enabled on CPU#0.\n");
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}
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