Thierry Reding a91bb605ec clk: tegra: Add sor_safe clock
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28 12:41:50 +02:00
..
2016-03-02 17:47:19 -08:00
2016-04-28 12:41:50 +02:00
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2016-03-02 17:47:19 -08:00
2016-04-28 12:41:50 +02:00