Oskar Schirmer
a81cbd2da4
xtensa: enforce slab alignment to maximum register width
...
XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.
Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now. But the S6000 variant will raise this to 16.
Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2009-04-02 23:41:16 -07:00
..
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