The primary aim of this patchset is to remove the pgprot_default and prot_sect_default global variables and rely strictly on predefined values. The original goal was to be able to run SMP kernels on UP hardware by not setting the Shareability bit. However, it is unlikely to see UP ARMv8 hardware and even if we do, the Shareability bit is no longer assumed to disable cacheable accesses. A side effect is that the device mappings now have the Shareability attribute set. The hardware, however, should ignore it since Device accesses are always Outer Shareable. Following the removal of the two global variables, there is some PROT_* macro reshuffling and cleanup, including the __PAGE_* macros (replaced by PAGE_*). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
400 lines
9.3 KiB
C
400 lines
9.3 KiB
C
/*
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* Based on arch/arm/mm/mmu.c
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*
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* Copyright (C) 1995-2005 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/nodemask.h>
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#include <linux/memblock.h>
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/sizes.h>
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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#include "mm.h"
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/*
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* Empty_zero_page is a special page that is used for zero-initialized data
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* and COW.
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*/
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struct page *empty_zero_page;
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EXPORT_SYMBOL(empty_zero_page);
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struct cachepolicy {
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const char policy[16];
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u64 mair;
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u64 tcr;
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};
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.mair = 0x44, /* inner, outer non-cacheable */
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.tcr = TCR_IRGN_NC | TCR_ORGN_NC,
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}, {
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.policy = "writethrough",
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.mair = 0xaa, /* inner, outer write-through, read-allocate */
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.tcr = TCR_IRGN_WT | TCR_ORGN_WT,
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}, {
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.policy = "writeback",
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.mair = 0xee, /* inner, outer write-back, read-allocate */
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.tcr = TCR_IRGN_WBnWA | TCR_ORGN_WBnWA,
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}
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};
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/*
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* These are useful for identifying cache coherency problems by allowing the
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* cache or the cache and writebuffer to be turned off. It changes the Normal
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* memory caching attributes in the MAIR_EL1 register.
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*/
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static int __init early_cachepolicy(char *p)
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{
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int i;
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u64 tmp;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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if (memcmp(p, cache_policies[i].policy, len) == 0)
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break;
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}
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if (i == ARRAY_SIZE(cache_policies)) {
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pr_err("ERROR: unknown or unsupported cache policy: %s\n", p);
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return 0;
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}
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flush_cache_all();
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/*
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* Modify MT_NORMAL attributes in MAIR_EL1.
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*/
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asm volatile(
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" mrs %0, mair_el1\n"
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" bfi %0, %1, #%2, #8\n"
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" msr mair_el1, %0\n"
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" isb\n"
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: "=&r" (tmp)
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: "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8));
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/*
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* Modify TCR PTW cacheability attributes.
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*/
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asm volatile(
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" mrs %0, tcr_el1\n"
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" bic %0, %0, %2\n"
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" orr %0, %0, %1\n"
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" msr tcr_el1, %0\n"
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" isb\n"
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: "=&r" (tmp)
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: "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK | TCR_ORGN_MASK));
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flush_cache_all();
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return 0;
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}
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early_param("cachepolicy", early_cachepolicy);
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pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot)
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{
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if (!pfn_valid(pfn))
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return pgprot_noncached(vma_prot);
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else if (file->f_flags & O_SYNC)
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return pgprot_writecombine(vma_prot);
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return vma_prot;
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}
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EXPORT_SYMBOL(phys_mem_access_prot);
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static void __init *early_alloc(unsigned long sz)
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{
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void *ptr = __va(memblock_alloc(sz, sz));
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memset(ptr, 0, sz);
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return ptr;
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}
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static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
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unsigned long end, unsigned long pfn)
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{
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pte_t *pte;
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if (pmd_none(*pmd)) {
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pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t));
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__pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE);
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}
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BUG_ON(pmd_bad(*pmd));
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pte = pte_offset_kernel(pmd, addr);
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do {
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set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC));
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pfn++;
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} while (pte++, addr += PAGE_SIZE, addr != end);
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}
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static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
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unsigned long end, phys_addr_t phys)
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{
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pmd_t *pmd;
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unsigned long next;
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/*
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* Check for initial section mappings in the pgd/pud and remove them.
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*/
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if (pud_none(*pud) || pud_bad(*pud)) {
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pmd = early_alloc(PTRS_PER_PMD * sizeof(pmd_t));
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pud_populate(&init_mm, pud, pmd);
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}
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pmd = pmd_offset(pud, addr);
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do {
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next = pmd_addr_end(addr, end);
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/* try section mapping first */
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if (((addr | next | phys) & ~SECTION_MASK) == 0) {
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pmd_t old_pmd =*pmd;
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set_pmd(pmd, __pmd(phys | PROT_SECT_NORMAL_EXEC));
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/*
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* Check for previous table entries created during
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* boot (__create_page_tables) and flush them.
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*/
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if (!pmd_none(old_pmd))
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flush_tlb_all();
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} else {
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alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys));
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}
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phys += next - addr;
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} while (pmd++, addr = next, addr != end);
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}
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static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
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unsigned long end, unsigned long phys)
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{
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pud_t *pud = pud_offset(pgd, addr);
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unsigned long next;
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do {
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next = pud_addr_end(addr, end);
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alloc_init_pmd(pud, addr, next, phys);
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phys += next - addr;
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} while (pud++, addr = next, addr != end);
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}
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/*
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* Create the page directory entries and any necessary page tables for the
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* mapping specified by 'md'.
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*/
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static void __init create_mapping(phys_addr_t phys, unsigned long virt,
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phys_addr_t size)
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{
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unsigned long addr, length, end, next;
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pgd_t *pgd;
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if (virt < VMALLOC_START) {
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pr_warning("BUG: not creating mapping for 0x%016llx at 0x%016lx - outside kernel range\n",
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phys, virt);
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return;
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}
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addr = virt & PAGE_MASK;
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length = PAGE_ALIGN(size + (virt & ~PAGE_MASK));
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pgd = pgd_offset_k(addr);
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end = addr + length;
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do {
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next = pgd_addr_end(addr, end);
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alloc_init_pud(pgd, addr, next, phys);
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phys += next - addr;
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} while (pgd++, addr = next, addr != end);
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}
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static void __init map_mem(void)
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{
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struct memblock_region *reg;
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phys_addr_t limit;
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/*
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* Temporarily limit the memblock range. We need to do this as
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* create_mapping requires puds, pmds and ptes to be allocated from
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* memory addressable from the initial direct kernel mapping.
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*
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* The initial direct kernel mapping, located at swapper_pg_dir,
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* gives us PGDIR_SIZE memory starting from PHYS_OFFSET (which must be
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* aligned to 2MB as per Documentation/arm64/booting.txt).
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*/
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limit = PHYS_OFFSET + PGDIR_SIZE;
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memblock_set_current_limit(limit);
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/* map all the memory banks */
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for_each_memblock(memory, reg) {
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phys_addr_t start = reg->base;
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phys_addr_t end = start + reg->size;
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if (start >= end)
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break;
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#ifndef CONFIG_ARM64_64K_PAGES
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/*
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* For the first memory bank align the start address and
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* current memblock limit to prevent create_mapping() from
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* allocating pte page tables from unmapped memory.
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* When 64K pages are enabled, the pte page table for the
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* first PGDIR_SIZE is already present in swapper_pg_dir.
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*/
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if (start < limit)
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start = ALIGN(start, PMD_SIZE);
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if (end < limit) {
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limit = end & PMD_MASK;
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memblock_set_current_limit(limit);
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}
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#endif
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create_mapping(start, __phys_to_virt(start), end - start);
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}
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/* Limit no longer required. */
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memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
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}
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/*
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* paging_init() sets up the page tables, initialises the zone memory
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* maps and sets up the zero page.
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*/
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void __init paging_init(void)
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{
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void *zero_page;
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map_mem();
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/*
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* Finally flush the caches and tlb to ensure that we're in a
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* consistent state.
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*/
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flush_cache_all();
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flush_tlb_all();
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/* allocate the zero page. */
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zero_page = early_alloc(PAGE_SIZE);
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bootmem_init();
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empty_zero_page = virt_to_page(zero_page);
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/*
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* TTBR0 is only used for the identity mapping at this stage. Make it
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* point to zero page to avoid speculatively fetching new entries.
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*/
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cpu_set_reserved_ttbr0();
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flush_tlb_all();
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}
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/*
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* Enable the identity mapping to allow the MMU disabling.
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*/
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void setup_mm_for_reboot(void)
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{
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cpu_switch_mm(idmap_pg_dir, &init_mm);
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flush_tlb_all();
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}
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/*
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* Check whether a kernel address is valid (derived from arch/x86/).
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*/
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int kern_addr_valid(unsigned long addr)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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if ((((long)addr) >> VA_BITS) != -1UL)
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return 0;
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pgd = pgd_offset_k(addr);
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if (pgd_none(*pgd))
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return 0;
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pud = pud_offset(pgd, addr);
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if (pud_none(*pud))
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return 0;
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pmd = pmd_offset(pud, addr);
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if (pmd_none(*pmd))
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return 0;
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if (pmd_sect(*pmd))
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return pfn_valid(pmd_pfn(*pmd));
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pte = pte_offset_kernel(pmd, addr);
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if (pte_none(*pte))
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return 0;
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return pfn_valid(pte_pfn(*pte));
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}
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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#ifdef CONFIG_ARM64_64K_PAGES
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int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
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{
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return vmemmap_populate_basepages(start, end, node);
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}
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#else /* !CONFIG_ARM64_64K_PAGES */
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int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
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{
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unsigned long addr = start;
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unsigned long next;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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do {
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next = pmd_addr_end(addr, end);
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pgd = vmemmap_pgd_populate(addr, node);
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if (!pgd)
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return -ENOMEM;
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pud = vmemmap_pud_populate(pgd, addr, node);
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if (!pud)
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return -ENOMEM;
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pmd = pmd_offset(pud, addr);
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if (pmd_none(*pmd)) {
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void *p = NULL;
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p = vmemmap_alloc_block_buf(PMD_SIZE, node);
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if (!p)
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return -ENOMEM;
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set_pmd(pmd, __pmd(__pa(p) | PROT_SECT_NORMAL));
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} else
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vmemmap_verify((pte_t *)pmd, node, addr, next);
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} while (addr = next, addr != end);
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return 0;
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}
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#endif /* CONFIG_ARM64_64K_PAGES */
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void vmemmap_free(unsigned long start, unsigned long end)
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{
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}
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#endif /* CONFIG_SPARSEMEM_VMEMMAP */
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