55148f6f88
Some ColdFire CPU UART hardware modules can configure the IRQ they use. Currently the same setup code is duplicated in the init code for each of these ColdFire CPUs. Merge all this code to a single instance. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/5307/config.c
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*
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* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2000, Lineo (www.lineo.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfwdebug.h>
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/***************************************************************************/
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/*
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* Some platforms need software versions of the GPIO data registers.
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*/
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unsigned short ppdata;
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unsigned char ledbank = 0xff;
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/***************************************************************************/
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static void __init m5307_timers_init(void)
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{
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/* Timer1 is always used as system timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER1ICR);
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mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
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#ifdef CONFIG_HIGHPROFILE
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/* Timer2 is to be used as a high speed profile timer */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
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MCF_MBAR + MCFSIM_TIMER2ICR);
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mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
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#endif
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}
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/***************************************************************************/
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void m5307_cpu_reset(void)
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{
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local_irq_disable();
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/* Set watchdog to soft reset, and enabled */
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__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
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for (;;)
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/* wait for watchdog to timeout */;
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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#if defined(CONFIG_NETtel) || \
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defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
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/* Copy command line from FLASH to local buffer... */
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memcpy(commandp, (char *) 0xf0004000, size);
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commandp[size-1] = 0;
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#endif
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mach_reset = m5307_cpu_reset;
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mach_sched_init = hw_timer_init;
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m5307_timers_init();
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/* Only support the external interrupts on their primary level */
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mcf_mapirq2imr(25, MCFINTC_EINT1);
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mcf_mapirq2imr(27, MCFINTC_EINT3);
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mcf_mapirq2imr(29, MCFINTC_EINT5);
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mcf_mapirq2imr(31, MCFINTC_EINT7);
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#ifdef CONFIG_BDM_DISABLE
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/*
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* Disable the BDM clocking. This also turns off most of the rest of
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* the BDM device. This is good for EMC reasons. This option is not
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* incompatible with the memory protection option.
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*/
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wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
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#endif
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}
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/***************************************************************************/
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