Kedareswara rao Appana 48c62fb051 dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma ... If the hardware is configured for Scatter Gather(SG) mode, and hardware is idle, in the control register SG mode bit must be set to a 0 then back to 1 by the software, to force the CDMA SG engine to use a new value written to the CURDESC_PNTR register, failure to do so could result errors from the dmaengine. This patch updates the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>		2018-01-08 16:24:50 +05:30
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Makefile	dmaengine: Add Xilinx zynqmp dma engine driver support	2016-07-08 11:25:34 +05:30
xilinx_dma.c	dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma	2018-01-08 16:24:50 +05:30
zynqmp_dma.c	dmaengine: zynqmp_dma: Fix race condition in the probe	2017-12-18 09:37:06 +05:30