Robin Murphy 205577ab6f iommu/io-pgtable-arm: Rationalise MAIR handling
Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2019-11-04 19:59:30 +00:00
..
2019-09-22 09:39:09 -07:00
2019-09-24 15:54:11 -07:00
2019-09-30 10:04:28 -07:00
2019-09-29 19:25:39 -07:00
2019-09-29 11:20:41 -07:00
2019-09-22 09:30:30 -07:00
2019-09-22 09:30:30 -07:00
2019-09-22 09:39:09 -07:00
2019-09-19 14:14:28 -07:00
2019-09-18 11:14:31 -07:00
2019-09-27 12:19:47 -07:00
2019-09-27 11:13:35 -07:00
2019-09-22 12:02:21 -07:00
2019-09-29 11:20:41 -07:00
2019-09-28 20:44:12 +02:00
2019-09-19 14:14:28 -07:00
2019-09-19 14:14:28 -07:00
2019-09-22 09:30:30 -07:00
2019-09-24 16:31:50 -07:00
2019-09-22 09:30:30 -07:00
2019-09-23 17:20:40 -04:00
2019-09-29 10:33:41 -07:00
2019-09-24 16:31:50 -07:00
2019-09-19 13:27:23 -07:00
2019-09-23 19:16:01 -07:00
2019-09-24 12:39:40 -07:00
2019-09-27 12:19:47 -07:00
2019-09-17 18:40:42 -07:00
2019-09-22 10:55:08 -07:00
2019-09-30 10:04:28 -07:00
2019-09-22 11:05:43 -07:00
2019-09-24 16:31:50 -07:00
2019-09-16 15:52:38 -07:00
2019-09-22 10:52:23 -07:00
2019-09-17 18:40:42 -07:00
2019-09-24 15:54:08 -07:00
2019-09-24 15:54:08 -07:00
2019-09-18 11:14:31 -07:00
2019-09-23 19:33:56 -07:00
2019-09-27 11:17:38 -07:00
2019-09-26 11:22:14 -07:00
2019-09-18 11:05:34 -07:00